Dear Altera experts,
My very first project is a PWM in Quartus II 7.0. I've drawn up a block diagram with a 17 bit lpm_counter going into a 5 bit lpm_compare. All I want is the top five bits of the counter to go into the comparator. After several days of trying I still have no idea how to split the 17 bits to just use the top five bits. With a normal bus connection it compiles with a Width mismatch error.
Peter
Hi Peter,
Draw a bus wire extending from the out of the counter and give it a name like counteroutput[17..0]. Draw another separate wire going into the lpm_compare and give it the name counteroutput[17..13]. They will be connected correctly by the extractor.
Hope this helps, Subroto Datta Altera Corp.
Prediction: One day you'll be *sooooo* sick of trying to maintain schematics that you'll bite the bullet and start to learn VHDL/Verilog...
Regards,
-- Mark McDougall, Engineer Virtual Logic Pty Ltd, 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
I think that you might be right. I haven't yet learned how to integrate the stuff I've learned in "Circuit Design with VHDL" with the Altera block schematics. Up until this month I mostly did C++ programming using emacs in a shell window. Then I got handed a NIOS II devkit and a September delivery deadline. At least "Fisher Price - My First PWM" now works many thanks to Subroto.
Peter
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