Hi,
I am thinking of using Verilog for a project I am working on. Originally I was going to use a processor core (and C) on an environment someone set up for me in VHDL/Verilog, then I thought of using FpgaC and doing it myself, and now I'm more or less decided on using Verilog to do most of it (minus the hardware stuff, after initial development and simulation).
My first questions, of which I hope there won't be many, relate to connecting 'wires' between modules, and simulations.
In my code I am attempting to change a value of 'addr' in setaddr to a specific value when processing starts, this will later be set by an address switch on the hardware. I am then trying to match this value in another module called decpacket when 'pktrx' changes, when a packet comes in (code not written for serial communications).
In ModelSim, the simulator shows that 'addr' in decpacket is 8 bits wide, but for some reason 'addr' in setaddr is only shown as a single bit. Could someone kindly point out what I am doing wrong, and how I can set this value in one location and use it in another?
Thanks,
RL
`timescale 1ns / 100ps
module setaddr(addr);
output[0:7] addr; reg addr;
initial begin addr = 8'd 1; end
endmodule
module decpacket (addr,pktrx,pkt,pkttype);
input[0:7] addr; input pktrx; input[0:95] pkt; output[0:7] pkttype;
reg pkttype;
always @(posedge pktrx) begin if(pkt[0:7] == addr) begin
end end
endmodule