Newbie: Slow FPGAs

I am probably opening a can of worms, but why are FPGAs so slow?

The CPU cores at

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represent an ever growing number of excellent and very practical, but slow processor implementations. What I mean is 240-500Mhz FPGAs, when market CPUs are in the 3Ghz range.

Surely there must be 1 or 2 Ghz FPGAs available with sub nano second gate switch/propagation times.

Or possibly it is a verilog, vhdl or synthesis problem with the designs?

Should I just use mass manufactured high speed CPUs and relegate the other discrete logic to CPLD/FPGAs??

Lastly, how fast is NIOSII?

Reply to
dave
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If you need huge processing speeds, "just use mass manufactured high speed CPUs."

If you want processing to augment your FPGA logic, consider adding a processor that adds functionality, not necessarily silicon-optimized speed. After all, how many DMIPs do you need?

Consider the 450 MHz PPC core in the Xilinx devices. That PPC405 core is running about as fast as you can get in any other PPC405 implementation. It

*is* optimized silicon.

The Intels and AMDs of this world typically produce designs that run in the

10s of watts. I want to run my FPGAs much cooler.

Modern FPGAs aren't slow. The processors you think of as "normal" speeds are just highly optimized.

Reply to
John_H

I quite agree with John_H its a mistake to compare FPGA functionality and CPU functionality,they are just fundamentaly different things.I also think its a mistake to implement a CPU in a FPGA but I'll prolly get flamed for saying that.

Reply to
Jezwold

Well I'm not really sure but this is what i think about your question:

  1. the first reason is that fpga are made to do all sort of design so you have route and interconnexion that consume time, in the case of a cpu you have a specific architecture so it can go faster (look at integrated multiplier in fpga go faster than if you implemented one in a fpga with lut and gate)

2.If you implement a specific algorithm in a fpga it will go faster than in a cpu because you can make hardware optimisation and where you could use 10 cycle with cpu it will need only 1 cycle in a fpga , and you could also implement many other processing unit, thing you could'nt do in a cpu I remember that during my courses of image processing that some algorithm in fpga @100MHz could process 1000*faster than a P4@2GHz

Frequency is not always the key look at AMD and Intel they are not running at the same frequency but they are both powerfull equivalent. And there is many other kind of CPU and also DSP.

3.I think Fast CPU instruction take also more cycle than soft CPU because of pipeline, so you go faster but you need more time(should i say cycle) to have your result , and in recursive computation it's a really annoying thing.

  1. If you run faster you also consume more current so for many application (as embedded) going faster is not an interesting

  2. comparing fpga and cpu is useless because they are not made for doing the same thing , CPU embedded in FPGA are more made to control other process and other task that don't need too much computation power comparing FPGA and CPU is like comparing plane and car

Regards

a écrit dans le message de news: d1cobl$rs6$ snipped-for-privacy@news8.svr.pol.co.uk...

Reply to
KCL

"Whoa there, hold your horses Tex!" What I consider "normal" speeds?!!?

I work with DSPs & parallel computers, however my home PCs max out at

700Mhz! It was a simple question, put your sword away.

You're correct. After all, why would Xilinx create a 450Mhz PPC core. Highly optimized to achieve.....

Anyway FPGAs are not for implementing processors. Bad idea right. They are just for combining discrete logic in a smaller space.

Contrary to what you may think there is a market for Ghz speed flexible FPGAs. But hey, what do I know, I am just a HDL newbie.

FlameOn buddy....

John_H wrote:

Reply to
dave

Ahhh! An answer that values my newbie-ness.

Ok, I think HDL and FPGA/CPLD is worth a look.

Reply to
dave

Honest question, why is it a mistake?

Reply to
dave

Ghz speed FPGAs with sub ns are seriously expensive,but as you say there must be a market otherwise they wouldnt make them. Ive just never come across anyone who used them to implement a general purpose CPU

Reply to
Jezwold

Thank you, I'm learning. (don't worry, I'll shut up soon!!)

Reply to
dave

Your 3GHz CPU can do a few adds or multiplies at 3GHz.

An FPGA can do hundreds or thousands of adds, or multiplies at a few hundred MHz. Which is faster?

-- glen

Reply to
glen herrmannsfeldt

Ok.... Thank you.

Reply to
dave

I completely agree. There is a market for GHz speed FPGAs. There's also a merket for TeraHertz speed processors. And a market for safe, $1500 cars.

Reply to
John_H

Couple of things

One factor affecting the speed of the circuit is the process. Some of the FPGAs like Virtex -II are fabricated in .13um technology abd are far behind the present CPU technology.

However, the latest FPGAs from Xilinx and Altera are 90nm (same as P4). I think the reason for the performance difference for these guys is, as u suggested, because of the tools. ASICs like CPUs are carefully optimized for area, timing, power and so on at every level. This is taken care of by the synthesis, PAR tools while designing the circuits using FPGAs. All you do is code the design and let the synthesizer, PAR tools do their best possible job. I also think this process is getting further complicated by the inherent design of the FPGAs.

Reply to
sam

Hi dave,

Embedded CPUs are 'hot' at the moment. In 1997 I implemented a PIC controller in an Altera Flex FPGA as a proof-of-concept. The implementation ran at three times the speed of the PIC, but cost $150, versus the $8 of the PIC.

Nowadays, FPGA gate pricing has come down to levels that make implementing a CPU on an FPGA economically viable. A NIOS II will easily fit into half an Altera EP1C3 FPGA costing around $12 (in low volume), leaving the other half for more specialized logic.

Then again, a PIC12/16/18 is available with lots of nice peripherals for prices around $6 or lower, so if you just want to use a CPU with some standard peripherals, then please just get a PIC (or a Cypress pSOC - they have a reprogrammable analog array as well!!).

If there's some nonstandard digital function you need to build, and there happens to be a CPU on the board you,re building as well, _then_ you may want to look whether you can stuff the CPU in an unused corner of your FPGA. Otherwise, just go dedicated.

Best regards,

Ben

Reply to
Ben Twijnstra

dynmic versus static hardware configuration. A road from your home to your work place can be a lot faster if you do not require it to be used by thousends of other people that use the same road for different routes. You can get a long without traffic lights, cross roads, and so on. The same for FPGAs they have switches were an asic has wires. So an fpga will have a slower cpu, than an cpu asic, and it will have a slower fir filter than an fir asic, but the fpga can do both the other two can't. For that reason often the fpga is faster. Because it is a faster cpu than the fir asic and a faster fir filter than the cpu asic.

Clock speed ist not everything. These people have a 90MHz FPGA ray tracing hardware that beats a P4-3GHz by a factor of four.

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The typical carry chain delay of an fpga is 50ps.

Kolja Sulimma

Reply to
Kolja Sulimma

Anyway it is strange why an PPC405 will only do ~500Mhz in 90nm in 2005 and a P4 in 90nm >3Ghz (factor 6 !!!), it suggests that the FPGA silicon is far less optimized as a CPU would, the process used for modern FPGA?s equals that of P4?s. Of course it all depends on the max level of logic between two clock levels expressed in FO4 delay's. The less levels the more though the design will be. A P4 is not a "though" design in this perspective and PPC405 also not, so still the question is why... Maybe the P4 is designed transistor by transistor, and a PPC405 in a V4 is only synthesized by some less efficient synthesis tools?? For sure it gives hope for the next generation FPGA?s.

Roel

Reply to
Roel

no it is not. Even outside fpgas the market share of slow processors is a lot larger than that of fast processors. For every 3GHz P4 there are dozens of 200MHz Riscs and hundreds of 10MHz MCUs sold. Why should Xilinx go for the exotic niche market that desktop PCs are from a processor builders view?

Both are optimized for different optimization goals. The PPC405 is by far smaller than a P4 and uses a lot less power. Here is a recent processor that the makers of the P4 consider highly optimized. It runs at up to 520MHz:

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Two P4 cores would burn more than a hundret watts. They would also need large caches, many io pins to access external memory quickly enough. (There is an empirical law in computer architecture that memory scales with performance.)

No, it used to be that DRAMs used the most advanced technology first, now that switches more and more to fpgas. CPU usually adopt the technology many months later.

Kolja Sulimma

Reply to
Kolja Sulimma

You need to be careful to compare BUS speeds, rather than CLK speeds. CLK speed can refer to how fast a single node in the chip toggles, (== marketing fluff) and on that basis, the FPGAs could be pitched at

10Ghz devices :) as the top end ones can do 10GHz comms....

Once you work at Bus-bandwidth numbers the differences greatly reduce and BUS bandwidth is also determined as much by memory devices, as it is by CPU/FPGA process. FPGAs have more general IOs, (and can easily make a BUS wider), whilst PCs try to save pins, and can focus the IO purely for DDR memory.

-jg

Reply to
Jim Granville

"Jezwold" schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...

Processing power isnt only defined by clock frequency.

Regards Falk

Reply to
Falk Brunner

I don't doubt it, but I suspect the market is unlikely to be satisfied with the cost/performance compromise.

Every gate in an FPGA costs...

- the gate itself (or LUT, or whatever)

- programming infrastructure to allow you to configure it

- programmable routing - that means switching matrices

- probably, some unused stuff around the gate because your chosen function doesn't fully occupy the FPGA cell (logic block, slice, whatever)

All these increase die area and therefore cost-per-function; some worsen signal delays as well. By contrast, a gate on a custom device is just that: a gate and some hardwired routing. It's sure to be faster than the FPGA equivalent.

There have been a few attempts, over the 20+year history of FPGAs, to introduce more ASIC-like structures in FPGA fabric. Most have failed horribly - remember Pilkington?

However, you can get amazing bang-per-buck in an FPGA if you use it to solve the right sort of problems. Any DSP-ish problem that keeps a lot of arithmetic units busy for a lot of the time will be a good candidate. Simple bit twiddling is always much faster in FPGAs than in programmable CPUs - try writing a piece of C to do this...

reg [15:0] R; ... R = {R[15:12], R[2:0], ~R[11:8], R[7:3]};

It's almost free in hardware, messy and slow in software.

And then the FPGA vendors have been very ingenious in adding a few dedicated functions that make it easier to map common problems on to the FPGA fabric. Embedded multipliers and RAMs are obvious examples. SERDES on I/O pins allows you to fan out a multi-GHz input to a much slower but wider data path in the FPGA fabric, and achieve stuff that would be impossible in software.

So, although I sense your frustration, things are probably the way they are for a good reason; and if you want 2GHz CPU then you better go and buy one from the usual suspects. I imagine that there will always be a factor of 10 difference between the fastest you can do a dedicated function in ASIC and the speed you can do the same thing in regular FPGA fabric.

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Reply to
Jonathan Bromley

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