Hi, I am a FPGA newbie. Here's my question: How do you count the gates in Xilinx FPGA? I have a XC3S400 board, which is supposed to have 400K gates. But when I synthesize the following code, the synthesizer report 68 LUTs were used, compared to total of 7168 LUTs, I would say that about 1% of the 400K gates, which is about 4000 gates, were used to synthesize my code. How ever, my following code only uses 150 "AND" gates and 142 "XOR" gates, why does it take XC3S400 take 4000 "gates" to handle my code? Is there any setting trick need to be done in the synthesizer or in the code?
//===============Verilog code=======================// module GFMul(z,y,x); output [7:0] z; input [7:0] y; input [7:0] x;
reg [7:0] z;
//entry: reg[7:0] t; always @(y or x ) begin
t[0]=((x [0]&y [0])^(x [1]&y [7])^(x [2]&y [6])^(x [3]&y [5])^(x [4]&y [4])^(x [5]&y [3])^(x [5]&y [7])^(x [6]&y [2])^(x [6]&y [6])^(x [6]&y [7])^(x [7]&y [1])^(x [7]&y [5])^(x [7]&y [6])^(x [7]&y [7])); t[1]=((x [0]&y [1])^(x [1]&y [0])^(x [2]&y [7])^(x [3]&y [6])^(x [4]&y [5])^(x [5]&y [4])^(x [6]&y [3])^(x [6]&y [7])^(x [7]&y [2])^(x [7]&y [6])^(x [7]&y [7])); t[2]=((x [0]&y [2])^(x [1]&y [1])^(x [1]&y [7])^(x [2]&y [0])^(x [2]&y [6])^(x [3]&y [5])^(x [3]&y [7])^(x [4]&y [4])^(x [4]&y [6])^(x [5]&y [3])^(x [5]&y [5])^(x [5]&y [7])^(x [6]&y [2])^(x [6]&y [4])^(x [6]&y [6])^(x [6]&y [7])^(x [7]&y [1])^(x [7]&y [3])^(x [7]&y [5])^(x [7]&y [6])); t[3]=((x [0]&y [3])^(x [1]&y [2])^(x [1]&y [7])^(x [2]&y [1])^(x [2]&y [6])^(x [2]&y [7])^(x [3]&y [0])^(x [3]&y [5])^(x [3]&y [6])^(x [4]&y [4])^(x [4]&y [5])^(x [4]&y [7])^(x [5]&y [3])^(x [5]&y [4])^(x [5]&y [6])^(x [5]&y [7])^(x [6]&y [2])^(x [6]&y [3])^(x [6]&y [5])^(x [6]&y [6])^(x [7]&y [1])^(x [7]&y [2])^(x [7]&y [4])^(x [7]&y [5])); t[4]=((x [0]&y [4])^(x [1]&y [3])^(x [1]&y [7])^(x [2]&y [2])^(x [2]&y [6])^(x [2]&y [7])^(x [3]&y [1])^(x [3]&y [5])^(x [3]&y [6])^(x [3]&y [7])^(x [4]&y [0])^(x [4]&y [4])^(x [4]&y [5])^(x [4]&y [6])^(x [5]&y [3])^(x [5]&y [4])^(x [5]&y [5])^(x [6]&y [2])^(x [6]&y [3])^(x [6]&y [4])^(x [7]&y [1])^(x [7]&y [2])^(x [7]&y [3])^(x [7]&y [7])); t[5]=((x [0]&y [5])^(x [1]&y [4])^(x [2]&y [3])^(x [2]&y [7])^(x [3]&y [2])^(x [3]&y [6])^(x [3]&y [7])^(x [4]&y [1])^(x [4]&y [5])^(x [4]&y [6])^(x [4]&y [7])^(x [5]&y [0])^(x [5]&y [4])^(x [5]&y [5])^(x [5]&y [6])^(x [6]&y [3])^(x [6]&y [4])^(x [6]&y [5])^(x [7]&y [2])^(x [7]&y [3])^(x [7]&y [4])); t[6]=((x [0]&y [6])^(x [1]&y [5])^(x [2]&y [4])^(x [3]&y [3])^(x [3]&y [7])^(x [4]&y [2])^(x [4]&y [6])^(x [4]&y [7])^(x [5]&y [1])^(x [5]&y [5])^(x [5]&y [6])^(x [5]&y [7])^(x [6]&y [0])^(x [6]&y [4])^(x [6]&y [5])^(x [6]&y [6])^(x [7]&y [3])^(x [7]&y [4])^(x [7]&y [5])); t[7]=((x [0]&y [7])^(x [1]&y [6])^(x [2]&y [5])^(x [3]&y [4])^(x [4]&y [3])^(x [4]&y [7])^(x [5]&y [2])^(x [5]&y [6])^(x [5]&y [7])^(x [6]&y [1])^(x [6]&y [5])^(x [6]&y [6])^(x [6]&y [7])^(x [7]&y [0])^(x [7]&y [4])^(x [7]&y [5])^(x [7]&y [6])); z =(t);
end
endmodule
//===============Resource Utilization================// Resource Usage Report for GFMul
Mapping to part: xc3s400tq144-4 LUT2 17 uses LUT3 9 uses LUT4 42 uses I/O primitives: 24 IBUF 16 uses OBUF 8 uses
I/O Register bits: 0 Register bits not including I/Os: 0 (0%)
Mapping Summary: Total LUTs: 68 (0%)
Thanks!