Hello all,
I'm a student, I didn't have any synthesis experience before, currently I need to perform VHDL to EDIF netlist format. The netlist file should be only limited to some specific resource, for example it contains only LUT after mapping, or only AND gates or NAND gates before mapping.
I already tried two synthesis tools, Xilinx XST and Synopsys Design Compiler. I can successfully got netlist in EDIF format. However, by checking user guide, I could not find how to constraint resource to a specific set of primitives in both XST and Synopsys DC. Does anyone know if this is possible?
Thanks in advance
Simin