Hi,
I have a quit simple question abaut cpld fitting: I'm using a Xilix Coolrunner (XPLA3) CPLD with pin locking and trying to access a SRAM. If I try to fit my code, the following error message is given by the fitter for some pins:
WARNING:Cpld:1081 - Cannot assign signal 'sram_data' to location '73=FB16_3'. Not enough control terms.
Searching the Xilinx answer data base I came across a posting (
Adjust the design to remove unnecessary unique control term usage (for example, use synchronous reset or preset as opposed to asynchronous reset or preset, and use synchronous load as opposed to asynchronous load).
Unfortunalty I don't know what a "synchronous reset or preset " means! Does this means that I have to have an synchronous reset for the cpld device (which I have) or does this mean that the macrocell itself should somehow be reseted synchonously? And how do I do that??
Thanks, Stephan
Part of my code:
--////////////////////////////////////////////////////////////////////////// ///////////////
--
-- BEGIN PROCESS MAIN
--
--////////////////////////////////////////////////////////////////////////// ///////////////
proc_main: process (CLK, RESET_not) is begin
--////////////////////////////////////////////////////////////////////////// ///////////////
--
-- CLK'event and CLK = '1'
--
--////////////////////////////////////////////////////////////////////////// ///////////////
if (CLK'event and CLK = '1') then
--////////////////////////////////////////////////////////////////////////// ///////////////
--
-- synchronous RESET
--
--////////////////////////////////////////////////////////////////////////// ///////////////
if RESET_not = '0' then -- usb EF_not