Newbie: Problems with clocks

Hello, I just got a new FPGA board (from Avnet, Xilinx Virtex4). The problem is that I never programmend a FPGA before. I use VHDL for programming and Precision from Mentor for synthesis. Xilinx ISE 7.1 is used for place-and-route. On the FPGA board is a push button. Within my VHDL code I defined a process, which is sensitive to the rising edge of the signal associated with that push button (I want to know, when the button is pushed).

pb_proc: process (push_button) is begin if push_button'event and push_button='1' then ....

The problem is, that Precision recognizes that signal and the associated pad as a clock input and the during place-and-route operation, ISE produces the following error message:

ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock IOB site The clock IOB component is placed at site IOB_X2Y112. The clock IO site can use the fast path between the IO and the Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. If this sub optimal condition is acceptable for this design you may set the environmentvariable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this message to a WARNING and allow your design to continue.

If I use the following constraint during synthesis, the error is reduced to a warning, but the input is still regarded as a clock. set_false_path -through { push_button } -design gatelevel

My questions are:

1) Is every input signal, to whose signal flanks the VHDL code is sensitive to, automatically a clock? What's the best way to prevent this during synthesis? Do I actually have to prevent it?

2) How can I set the environmentvariable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING? I'm using the Linux version of ISE and using ISE from within Precision. I'm sure that there is a menu entry to set that variable, but I don't start ISE direct, but from within Precision. So I'd like to know in which configuration file I can place that variable setting. Also I'd like to know which additional environmentvaribles exist. I couldn't find a list or anything in the documentation.

Thank you,

Andreas

P.S.: another question of topi: When I setup my Design, I have to chose technology(Virtex-IV), Device(4vlx25ff668) and Speed Grade(-10 or -11). Which speed grade do I have to choose? Does the board support -10 and -11? Whats better? What is the speed grade exactly? Do I have to/Can I determin the supported speed grades of my board somehow?

Reply to
Andreas
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You got this error because your VHDL instantiates a flip-flop whose clock is the signal push_button, and your constraints told the tools to put the signal push_button onto a pin that's not a global clock pin.

You should spend some quality time with the XST manual, especially the sections that detail how certain structures are inferred from VHDL.

I'm not quite sure what you mean by "whose signal flanks the VHDL code is sensitive to." My English parser threw a rod on that one.

prevent it?

As I said above, your VHDL process above creates a clocked flip-flop. Write proper code and the error will go away.

Environment variables can be set from the shell command-line, or through a .bashrc or .cshrc or other script. The syntax is shell-dependent, so you should probably check the documentation for your particular shell.

Choose the speed grade that matches the device installed on your board.

Dunno, look at the chip, or read the documents that came with your board.

Speed grade roughly indicates the FPGA's maximum speed. Read the Virtex docs to determine whether the higher number (-11 versus -10) is faster or slower. If your design doesn't require the highest clock frequency, you can save money by choosing a slower part. This is relevant if you're building your own boards.

You must know the speed grade of the parts with which you're designing. And to determine the speed grade of the part on your board, RTFM.

-a

Reply to
Andy Peters

The instantiation of a flip-flop is exactly what I wanted as well as the connection between the push_button and the clock input of the flip-flop. The only thing I don't want is that the synthesis tool treats the push_button as an external clock input although it is connected to the clock input of a flip-flop. I've read the documentation before I wrote any posting, but I couldn't find the answers I need.

Do not know it.

I did it before my posting, but coudn't find any information.

Thanks, Andreas

Reply to
Andreas

Hi Andreas, I don't know how to do it in Precision but in XST you can tell the tool to use no GlobalClockBuffer at all (Xilinx Specific Options Tab). Then any Input can be (ab)used as a Clock input using normal routing resoources instead the global clock net. For one FF and Testing this might be OK. In a large design you will get into big trouble.

Now, If you are a newbie you brobably intend to use the button for manual clocking, to allow single stepping of your design. Beware!!!

Just imagine a simple counter driving some LEDs. What you expect is that it increments with every press on the button. But what happens will be random outputs to appear on your LEDs. Why is that? Because your Button bounces several times each time you press it and/or release it. Not very usefull, is it?

To overcome this problem you need two things: One is a clock divider driven by the onboard Clock Oscillator. The Output can be something about 100Hz and needs only to create an impulse of a single clocks length.

This signal can be used as a clock enable for a debouncing circuit which is described in the Xilinx synthesis template. Then you can use your button(s) for Input, and even (ab)use this Output signal as a Clock Signal. But remember: Only for testing SMALL designs! You also need to constrain the number of GCLK Buffers to 1.

Have a nice Synthesis

Eilert

Reply to
backhus

Thank you for that information. The example you describe is exact the test case I wanted to use in my first FPGA test design.

Greetings, Andreas

Reply to
Andreas

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