[Newbie] Microblaze and uC/OS-II on Spartan3

Hi all

I'm a student and newbie in FPGA design

I have a port of uC/OS-II on Memec Virtex-II MB1000 Development Ki from the Micrium's website and i want to port it on a Spartan3 Boar from Digilen

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All services of the OS are disabled. There is only 1 task and print The program size is 21 KB. On S3, there is 216Kbits/27KB of BRAM In parameters Tab of EDK, i set C_MEMSIZE if Bram to 27000 and my bot lmb controller to 16KB (max). I have always ".elf cannot resid completely in bram", i set microblaze_0_bootloop to "marked t initialize BRAMs" and follow the instructions as written in man tutorials for debugging. XMD told me : "unable to stop Microblaze verify if FPGA is configured and Microblaze system clock is connecte properly". I have change the .ucf fil to correspond with my card and the system clock is set

Are there other files to change? Could someone help me to understan

that is wrong

Thanks for your answer

Reply to
Gog
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Hi,

You can't get a 21kbyte program into a 16kbyte memory. The memory blocks in EDK can only have the size of 2**N so you need two memory blocks, one of 16kbyte and one of 8 kbyte. This should give you enough memory.

But I would suggest that you starting to use the external memory on the board.

On the problem with debugging, much more information is needed about your system. Have you enabled HW debug logic on MicroBlaze?

Göran

Reply to
Göran Bilski

Hi

It's very odd and frustrating, if i start with the port on memec,

have to change the IDCODE in a .bsd fil

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and i can't debug; if i start with an example from Xilinx, which work fine in SRAM and i modify it to include the sources of uC/OS-II, can't build the system :

/xygdrive/c/DOCUME~1/GAILLI~1/LOCALS~1/Temp/ccvN6OEm.s: Assemble

messages /xygdrive/c/DOCUME~1/GAILLI~1/LOCALS~1/Temp/ccvN6OEm.s:339: Error Variable is accessed using small data read write anchor, but it i not in the small data read write sectio

Any suggestions

Reply to
Gog

Thank you Mr. Bilski

two memory

The .elf can reside in bram and my project is "marked to initialis

BRAMs"

the board

With SRAM or only BRAMs, i have the same problem concerning th

debugging

"Unable to Stop MicroBlaz

Verify if FPGA is configured and MicroBlaze System Clock is connecte properl Unable to connect to MicroBlaze

your system

I don't know exactly what does "HW debug logic enabling" mean, but

have a debug_module connected to microblaze. Concerning my syste with brams, here is my .mhs

PARAMETER VERSION = 2.1.

PORT tx = tx, DIR = OU

PORT sys_rst = sys_rst_s, DIR = I PORT sys_clk = sys_clk_s, DIR = IN, SIGIS = CL PORT sw = sw, VEC = [0:7], DIR = I PORT rx = rx, DIR = I

BEGIN opb_uartlit

PARAMETER INSTANCE = myuar PARAMETER HW_VER = 1.00. PARAMETER C_DATA_BITS = PARAMETER C_CLK_FREQ = 5000000 PARAMETER C_BAUDRATE = 5760 PARAMETER C_USE_PARITY = PARAMETER C_ODD_PARITY = PARAMETER C_BASEADDR = 0x8000200 PARAMETER C_HIGHADDR = 0x800020f BUS_INTERFACE SOPB = myop PORT TX = t PORT RX = r EN

BEGIN opb_time

PARAMETER INSTANCE = mytimer PARAMETER HW_VER = 1.00. PARAMETER C_BASEADDR = 0x8000210 PARAMETER C_HIGHADDR = 0x800021f BUS_INTERFACE SOPB = myop PORT Interrupt = timer PORT CaptureTrig0 = net_gn EN

BEGIN opb_time

PARAMETER INSTANCE = mytimer PARAMETER HW_VER = 1.00. PARAMETER C_BASEADDR = 0x8000220 PARAMETER C_HIGHADDR = 0x800022f BUS_INTERFACE SOPB = myop PORT CaptureTrig0 = net_gn PORT Interrupt = timer EN

BEGIN opb_v2

PARAMETER INSTANCE = myop PARAMETER HW_VER = 1.10. PARAMETER C_EXT_RESET_HIGH = PORT OPB_Clk = sys_clk_ PORT SYS_Rst = sys_rst_ EN

BEGIN opb_int

PARAMETER INSTANCE = myint PARAMETER HW_VER = 1.00. PARAMETER C_BASEADDR = 0x8000230 PARAMETER C_HIGHADDR = 0x800023f BUS_INTERFACE SOPB = myop PORT Intr = timer1 & timer PORT Irq = interrup EN

BEGIN opb_gpi

PARAMETER INSTANCE = mygpio_ PARAMETER HW_VER = 3.01. PARAMETER C_GPIO_WIDTH = PARAMETER C_ALL_INPUTS = PARAMETER C_BASEADDR = 0x8000240 PARAMETER C_HIGHADDR = 0x800025f BUS_INTERFACE SOPB = myop PORT GPIO_IO = s EN

BEGIN microblaz

PARAMETER INSTANCE = mblaz PARAMETER HW_VER = 2.10. PARAMETER C_USE_BARREL = PARAMETER C_FSL_LINKS = PARAMETER C_FSL_DATA_SIZE = 3 PARAMETER C_DEBUG_ENABLED = PARAMETER C_USE_MSR_INSTR = PARAMETER C_NUMBER_OF_PC_BRK = PARAMETER C_NUMBER_OF_RD_ADDR_BRK = PARAMETER C_NUMBER_OF_WR_ADDR_BRK = BUS_INTERFACE DLMB = d_lm BUS_INTERFACE ILMB = i_lm BUS_INTERFACE DOPB = myop BUS_INTERFACE IOPB = myop PORT DBG_REG_EN = DBG_REG_EN_ PORT DBG_TDO = DBG_TDO_ PORT DBG_UPDATE = DBG_UPDATE_ PORT DBG_TDI = DBG_TDI_ PORT INTERRUPT = interrup PORT DBG_CLK = DBG_CLK_ PORT DBG_CAPTURE = DBG_CAPTURE_ PORT CLK = sys_clk_ EN

BEGIN lmb_bram_if_cntl

PARAMETER INSTANCE = islm PARAMETER HW_VER = 1.00. PARAMETER C_BASEADDR = 0x0000000 PARAMETER C_HIGHADDR = 0x00003ff BUS_INTERFACE SLMB = i_lm BUS_INTERFACE BRAM_PORT = port EN

BEGIN lmb_v1

PARAMETER INSTANCE = i_lm PARAMETER HW_VER = 1.00. PARAMETER C_EXT_RESET_HIGH = PORT SYS_Rst = sys_rst_ PORT LMB_Clk = sys_clk_ EN

BEGIN lmb_bram_if_cntl

PARAMETER INSTANCE = dslm PARAMETER HW_VER = 1.00. PARAMETER C_BASEADDR = 0x0000000 PARAMETER C_HIGHADDR = 0x00003ff BUS_INTERFACE SLMB = d_lm BUS_INTERFACE BRAM_PORT = port EN

BEGIN opb_md

PARAMETER INSTANCE = debug_modul PARAMETER HW_VER = 2.00. PARAMETER C_MB_DBG_PORTS = PARAMETER C_USE_UART = PARAMETER C_UART_WIDTH = PARAMETER C_BASEADDR = 0x8000260 PARAMETER C_HIGHADDR = 0x800026f BUS_INTERFACE SOPB = myop PORT OPB_Clk = sys_clk_ PORT DBG_UPDATE_0 = DBG_UPDATE_ PORT DBG_CLK_0 = DBG_CLK_s PORT DBG_TDO_0 = DBG_TDO_s PORT DBG_TDI_0 = DBG_TDI_s PORT DBG_CAPTURE_0 = DBG_CAPTURE_s PORT DBG_REG_EN_0 = DBG_REG_EN_s END

BEGIN lmb_v10 PARAMETER INSTANCE = d_lmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_s END

BEGIN bram_block PARAMETER INSTANCE = bram1 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTB = portb BUS_INTERFACE PORTA = porta END

BEGIN bram_block PARAMETER INSTANCE = bram2 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = porta2 BUS_INTERFACE PORTB = portb2 END

BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = islmb2 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00006000 PARAMETER C_HIGHADDR = 0x00007fff BUS_INTERFACE SLMB = i_lmb BUS_INTERFACE BRAM_PORT = porta2 END

BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dslmb2 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00006000 PARAMETER C_HIGHADDR = 0x00007fff BUS_INTERFACE SLMB = d_lmb BUS_INTERFACE BRAM_PORT = portb2 END

I hope it will help you...

Reply to
Gog

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