newbie ABEL questions

Hi, All:

I am quite new to ABEL HDL, I am debugging a digital design and come across following code.

...

IACK PIN 13;

INT5 NODE ISTYPE 'REG'; IVEC NODE;

EQUATIONS

INT5 := 0; INT5.LH = IVEC; INT5.RE = !IACK;

...

So, is INT5 a gated S-R Latch? if not, what is it? what will be the truth table? Seems to me INT5 will remain 0 forever.

Regards

Mark

Reply to
Mark Linn
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Ok, my boss gave me the wrong code.

The correct one is: ... INT5 := 1; ...

It makes sense now.

Reply to
Mark Linn

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