Newbee Microblaze system BRAM utlization confusion

Hi All ,

I am new to FPGA development and have learned VHDL using text books. NOW! that doesn't teach practical aspects! I am extremely confused with the following discovery -

I am using Spartan 3 400k device and it has 16 block rams. I have configured a microblaze system to use block ram as follows -

1) Local memory - 16 Kbytes 2) OPB Block Ram 1 - 8Kbytes 3) OPB Block Ran 2 - 8Kbytes

That means that it has used up all the block Rams.

Now the confusing part - I have designed an IP which consumes 15 Block Rams , and when I include the IP in my microblaze system , the bitstream gets generated! The synthesis report shows that my IP is using up 15 Block Rams and that microblaze momories are using up 16 Block Rams! That means that the system is using up 31 Block Rams!

How is that Possilbe?

Any help would be greatly appreciated.

BR Rate

Reply to
ratemonotonic
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Hi,

Can you show the system.mhs file and the system_map.mrp contents?

You can't have 31 BRAMs in a device with 16 BRAMs. There is no extra magic inside the FPGA, just the usual magic.

Göran

Reply to
Göran Bilski

The final synthesis report probably shows about 190% of the BRAM resources are used.

The synthesis output is valid - BUT - will not pass through the implementation tools until you either: redesign to use fewer resources, or: target a bigger FPGA.

If you don't want to re-design, low cost boards are available with the Spartan-3 1500. Here's one...

formatting link

- Brian

Reply to
Brian Drummond

yes it is confusing because I am able to burn the logic and step through the C code! The system.mhh is as follows -

# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 9.2 Build EDK_Jm.16 # Tue Dec 11 11:23:35 2007 # Target Board: Memec Spartan-3 3S400LC Development Board Rev 2 # Family: spartan3 # Device: XC3S400 # Package: PQ208 # Speed Grade: -4 # Processor: microblaze_0 # System clock frequency: 50.000000 MHz # On Chip Memory : 16 KB # ############################################################################## PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O PORT fpga_0_DIP_Switches_4Bit_GPIO_in_pin = fpga_0_DIP_Switches_4Bit_GPIO_in, DIR = I, VEC = [0:3] PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =

50000000 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST

BEGIN microblaze PARAMETER HW_VER = 7.00.a PARAMETER INSTANCE = microblaze_0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_AREA_OPTIMIZED = 1 PARAMETER C_FSL_LINKS = 1 PARAMETER C_FAMILY = spartan3 PARAMETER C_INSTANCE = microblaze_0 BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb BUS_INTERFACE DEBUG = microblaze_0_dbg BUS_INTERFACE SFSL0 = modem_fsl_wrapper_0_to_microblaze_0_0 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE MFSL0 = microblaze_0_to_modem_fsl_wrapper_0_0 PORT RESET = mb_reset PORT INTERRUPT = microblaze_0_INTERRUPT END

BEGIN plb_v46 PARAMETER INSTANCE = mb_plb PARAMETER HW_VER = 1.00.a PORT PLB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END

BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END

BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END

BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007FFF BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_cntlr_BRAM_PORT END

BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007FFF BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_cntlr_BRAM_PORT END

BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTB = dlmb_cntlr_BRAM_PORT BUS_INTERFACE PORTA = ilmb_cntlr_BRAM_PORT END

BEGIN xps_uartlite PARAMETER INSTANCE = RS232 PARAMETER HW_VER = 1.00.a PARAMETER C_BAUDRATE = 9600 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000 PARAMETER C_BASEADDR = 0x83c12000 PARAMETER C_HIGHADDR = 0x83c121ff BUS_INTERFACE SPLB = mb_plb PORT RX = fpga_0_RS232_RX PORT TX = fpga_0_RS232_TX END

BEGIN xps_gpio PARAMETER INSTANCE = DIP_Switches_4Bit PARAMETER HW_VER = 1.00.a PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_IS_DUAL = 0 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_IS_BIDIR = 0 PARAMETER C_BASEADDR = 0x81400000 PARAMETER C_HIGHADDR = 0x8140ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_in = fpga_0_DIP_Switches_4Bit_GPIO_in END

BEGIN xps_timer PARAMETER INSTANCE = timer_counter PARAMETER HW_VER = 1.00.a PARAMETER C_ONE_TIMER_ONLY = 1 PARAMETER C_BASEADDR = 0x83c00000 PARAMETER C_HIGHADDR = 0x83c0ffff BUS_INTERFACE SPLB = mb_plb PORT Interrupt = timer1 PORT CaptureTrig0 = net_gnd END

BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_CLKIN_FREQ = 50000000 PARAMETER C_CLKOUT0_FREQ = 50000000 PARAMETER C_CLKOUT0_PHASE = 0 PARAMETER C_CLKOUT0_GROUP = NONE PORT CLKOUT0 = sys_clk_s PORT CLKIN = dcm_clk_s PORT LOCKED = Dcm_all_locked PORT RST = net_gnd END

BEGIN mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 1.00.a PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x84400000 PARAMETER C_HIGHADDR = 0x8440ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg PORT Debug_SYS_Rst = Debug_SYS_Rst END

BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER HW_VER = 2.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT Slowest_sync_clk = sys_clk_s PORT Dcm_locked = Dcm_all_locked PORT Ext_Reset_In = sys_rst_s PORT MB_Reset = mb_reset PORT Bus_Struct_Reset = sys_bus_reset PORT MB_Debug_Sys_Rst = Debug_SYS_Rst END

BEGIN fsl_v20 PARAMETER INSTANCE = modem_fsl_wrapper_0_to_microblaze_0_0 PARAMETER HW_VER = 2.11.a PORT FSL_Clk = sys_clk_s PORT SYS_Rst = net_gnd END

BEGIN modem_fsl_wrapper PARAMETER INSTANCE = modem_fsl_wrapper_0 BUS_INTERFACE MFSL = modem_fsl_wrapper_0_to_microblaze_0_0 BUS_INTERFACE SFSL = microblaze_0_to_modem_fsl_wrapper_0_0 PORT FSL_Clk = sys_clk_s END

BEGIN fsl_v20 PARAMETER INSTANCE = microblaze_0_to_modem_fsl_wrapper_0_0 PARAMETER HW_VER = 2.11.a PORT FSL_Clk = sys_clk_s PORT SYS_Rst = net_gnd END

BEGIN xps_intc PARAMETER INSTANCE = xps_intc_0 PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x83c14000 PARAMETER C_HIGHADDR = 0x83c141ff BUS_INTERFACE SPLB = mb_plb PORT Irq = microblaze_0_INTERRUPT PORT Intr = timer1 END

BEGIN util_vector_logic PARAMETER INSTANCE = util_vector_logic_0 PARAMETER HW_VER = 1.00.a END

The guilty modules are -

1)modem_fsl_wrapper whose device utilisation summary is - Selected Device : 3s400pq208-4

Number of Slices: 665 out of 3584 18% Number of Slice Flip Flops: 841 out of 7168 11% Number of 4 input LUTs: 995 out of 7168 13% Number used as logic: 923 Number used as Shift registers: 72 Number of IOs: 140 Number of bonded IOBs: 0 out of 141 0% Number of BRAMs: 15 out of 16 93% Number of MULT18X18s: 16 out of 16 100% Number of GCLKs: 6 out of 8 75%

2) Local BRAM - device utilisatioin - Device utilization summary:

---------------------------

Selected Device : 3s400pq208-4

Number of Slices: 0 out of 3584 0% Number of IOs: 206 Number of bonded IOBs: 0 out of 141 0% Number of BRAMs: 16 out of 16 100%

Thanks for the guidance ! BR Rate

Reply to
ratemonotonic

yes it is confusing because I am able to burn the logic and step through the C code! The system.mhh is as follows -

# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 9.2 Build EDK_Jm.16 # Tue Dec 11 11:23:35 2007 # Target Board: Memec Spartan-3 3S400LC Development Board Rev 2 # Family: spartan3 # Device: XC3S400 # Package: PQ208 # Speed Grade: -4 # Processor: microblaze_0 # System clock frequency: 50.000000 MHz # On Chip Memory : 16 KB # ############################################################################## PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O PORT fpga_0_DIP_Switches_4Bit_GPIO_in_pin = fpga_0_DIP_Switches_4Bit_GPIO_in, DIR = I, VEC = [0:3] PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =

50000000 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST

BEGIN microblaze PARAMETER HW_VER = 7.00.a PARAMETER INSTANCE = microblaze_0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_AREA_OPTIMIZED = 1 PARAMETER C_FSL_LINKS = 1 PARAMETER C_FAMILY = spartan3 PARAMETER C_INSTANCE = microblaze_0 BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb BUS_INTERFACE DEBUG = microblaze_0_dbg BUS_INTERFACE SFSL0 = modem_fsl_wrapper_0_to_microblaze_0_0 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE MFSL0 = microblaze_0_to_modem_fsl_wrapper_0_0 PORT RESET = mb_reset PORT INTERRUPT = microblaze_0_INTERRUPT END

BEGIN plb_v46 PARAMETER INSTANCE = mb_plb PARAMETER HW_VER = 1.00.a PORT PLB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END

BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END

BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END

BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007FFF BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_cntlr_BRAM_PORT END

BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007FFF BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_cntlr_BRAM_PORT END

BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTB = dlmb_cntlr_BRAM_PORT BUS_INTERFACE PORTA = ilmb_cntlr_BRAM_PORT END

BEGIN xps_uartlite PARAMETER INSTANCE = RS232 PARAMETER HW_VER = 1.00.a PARAMETER C_BAUDRATE = 9600 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000 PARAMETER C_BASEADDR = 0x83c12000 PARAMETER C_HIGHADDR = 0x83c121ff BUS_INTERFACE SPLB = mb_plb PORT RX = fpga_0_RS232_RX PORT TX = fpga_0_RS232_TX END

BEGIN xps_gpio PARAMETER INSTANCE = DIP_Switches_4Bit PARAMETER HW_VER = 1.00.a PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_IS_DUAL = 0 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_IS_BIDIR = 0 PARAMETER C_BASEADDR = 0x81400000 PARAMETER C_HIGHADDR = 0x8140ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_in = fpga_0_DIP_Switches_4Bit_GPIO_in END

BEGIN xps_timer PARAMETER INSTANCE = timer_counter PARAMETER HW_VER = 1.00.a PARAMETER C_ONE_TIMER_ONLY = 1 PARAMETER C_BASEADDR = 0x83c00000 PARAMETER C_HIGHADDR = 0x83c0ffff BUS_INTERFACE SPLB = mb_plb PORT Interrupt = timer1 PORT CaptureTrig0 = net_gnd END

BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_CLKIN_FREQ = 50000000 PARAMETER C_CLKOUT0_FREQ = 50000000 PARAMETER C_CLKOUT0_PHASE = 0 PARAMETER C_CLKOUT0_GROUP = NONE PORT CLKOUT0 = sys_clk_s PORT CLKIN = dcm_clk_s PORT LOCKED = Dcm_all_locked PORT RST = net_gnd END

BEGIN mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 1.00.a PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x84400000 PARAMETER C_HIGHADDR = 0x8440ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg PORT Debug_SYS_Rst = Debug_SYS_Rst END

BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER HW_VER = 2.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT Slowest_sync_clk = sys_clk_s PORT Dcm_locked = Dcm_all_locked PORT Ext_Reset_In = sys_rst_s PORT MB_Reset = mb_reset PORT Bus_Struct_Reset = sys_bus_reset PORT MB_Debug_Sys_Rst = Debug_SYS_Rst END

BEGIN fsl_v20 PARAMETER INSTANCE = modem_fsl_wrapper_0_to_microblaze_0_0 PARAMETER HW_VER = 2.11.a PORT FSL_Clk = sys_clk_s PORT SYS_Rst = net_gnd END

BEGIN modem_fsl_wrapper PARAMETER INSTANCE = modem_fsl_wrapper_0 BUS_INTERFACE MFSL = modem_fsl_wrapper_0_to_microblaze_0_0 BUS_INTERFACE SFSL = microblaze_0_to_modem_fsl_wrapper_0_0 PORT FSL_Clk = sys_clk_s END

BEGIN fsl_v20 PARAMETER INSTANCE = microblaze_0_to_modem_fsl_wrapper_0_0 PARAMETER HW_VER = 2.11.a PORT FSL_Clk = sys_clk_s PORT SYS_Rst = net_gnd END

BEGIN xps_intc PARAMETER INSTANCE = xps_intc_0 PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x83c14000 PARAMETER C_HIGHADDR = 0x83c141ff BUS_INTERFACE SPLB = mb_plb PORT Irq = microblaze_0_INTERRUPT PORT Intr = timer1 END

BEGIN util_vector_logic PARAMETER INSTANCE = util_vector_logic_0 PARAMETER HW_VER = 1.00.a END

The guilty modules are -

1)modem_fsl_wrapper whose device utilisation summary is - Selected Device : 3s400pq208-4

Number of Slices: 665 out of 3584 18% Number of Slice Flip Flops: 841 out of 7168 11% Number of 4 input LUTs: 995 out of 7168 13% Number used as logic: 923 Number used as Shift registers: 72 Number of IOs: 140 Number of bonded IOBs: 0 out of 141 0% Number of BRAMs: 15 out of 16 93% Number of MULT18X18s: 16 out of 16 100% Number of GCLKs: 6 out of 8 75%

2) Local BRAM - device utilisatioin - Device utilization summary:

---------------------------

Selected Device : 3s400pq208-4

Number of Slices: 0 out of 3584 0% Number of IOs: 206 Number of bonded IOBs: 0 out of 141 0% Number of BRAMs: 16 out of 16 100%

Thanks for the guidance ! BR Rate

Reply to
ratemonotonic

spartan 3 400 has 56Kbit distributed RAM is it possible that the synthesizer is using then as block RAMs as well?

BR Rate

Reply to
ratemonotonic

Look at the map report and see what utilization it reports. Many optimizations are performed in the map phase, including removing unconnected/unused resources. It may be that something is not connected the way you meant it to be, and map is removing it. This can happen during development if not all of your signals are connected yet.

If that is the case, it may not help your situation of wanting to use more BRAMS than are in the device, but it explains why your design made it through place and route.

Regards,

John McCaskill

Reply to
John McCaskill

I'll have to remember that one! :-)

Reply to
Eric Smith

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Hi,

From your email I found this. It looks everything has been trimmed away since you are using 0% slices = and 0 pads.

If you look at the system_map.mrp file, there is a section on what has = been trimmed away. That could give you a hint what is causing this. You might also add the = option "-detail" to the map tool.

G=F6ran

Device utilization summary:

Reply to
Göran Bilski

Not if your design specifically calls for BRAMS, so not likely. In any case it would appear in the synth report and map.mrp as "LUTs used as memory" or equivalent wording.

I am confused by the separate synthesis reports yu posted for modem_wrapper and local_bram ... are you synthesising the two separately? If so, how are you combining them into one project?

Is this built entirely under EDK or are you combining an EDK design with an XST design? It is possible that something is going wrong with that step; apparently leaving you with a working Microblaze so presumably no modem... you have to get through this step to correctly fail, THEN worry about economising memory.

- Brian

Reply to
Brian Drummond

Thanks for all the useful messages , I have clarified the base system and connected all the External IOs in the UCF and the synthesis is failing. I will be designing SRAM and FLASH to the design for software and use the internal block rams for local memory , cache and Hardware usage.

I am learning more an more about synthesis tools and I am starting to like this!

Thanks Niladri

Reply to
ratemonotonic

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