Hey all:
I'm working with Altera's Stratix 1S40 dev kit, and am debugging a CMOS sensor interface where the FSM that control's the FIFO appears to be in no state. The purpose of this CMOS sensor interface is to simply take the 16-bit data from the sensor on every rising edge of the pixel clock (27 MHz) and make it available to the Nios 2 processor (via the Avalon bus; ~50 MHz).
To this end, I've used a dual clock FIFO, with the write port connected to the sensor, and the read port to the avalon interface (+ glue logic, of course). I also have a 3-state FSM (to control the FIFO) that (state
1) simply waits for the frame from the sensor to become valid, then (state 2) wait for the horizontal line to be valid and finally (state 3) writes to the fifo until its full.Now the problem appears when I use Nios to transfer the contents of the FIFO directly to the UART (and to a computer for some post-processing); after a few 1000 pixels (around 15% of the total), the stream of data to the computer stops. After some debugging with Nios' GDB/Eclipse getup and SignalTap it appears that the constructed FSM is in no state (since the signaltap signals . for each of the 3 states were low).
During the compilation process, I received no warnings/errors regarding timing constraints etc. or anything else for that matter. I am at a complete loss as to how to even begin fixing this. Thoughts anyone?
Thanks in advance,
James