I want to instantiate some CoreGen modules to get some usage estimates on some possible target platforms. I've never created a project from scratch, I've only used vendor supplied projects to implement my designs, so I'm lost .
Here's my entity w/ instantiation:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY unisim; USE unisim.vcomponents.ALL;
entity coreest is port ( clk_in: in std_logic; reset: in std_logic; din: in std_logic_vector(15 downto 0); dout: out std_logic_vector(15 downto 0) ); end coreest;
architecture str_ar of coreest is
component BUFG is port ( I : in std_logic; O : out std_logic ); end component;
component macfir port ( CLK: IN std_logic; RESET: IN std_logic; ND: IN std_logic; RDY: OUT std_logic; RFD: OUT std_logic; DIN: IN std_logic_VECTOR(15 downto 0); DOUT: OUT std_logic_VECTOR(37 downto 0)); end component;
signal clk: std_logic;
signal macfir_nd: std_logic; signal macfir_din: std_logic_vector(15 DOWNTO 0); signal macfir_rdy: std_logic; signal macfir_rfd: std_logic; signal macfir_dout: std_logic_vector(37 DOWNTO 0);
begin
clk_in_bufg_inst : BUFG port map( I => clk_in, O => clk );
macfir_inst : macfir port map ( CLK => clk, RESET => reset, ND => macfir_nd, DIN => macfir_din, RDY => macfir_rdy, RFD => macfir_rfd, DOUT => macfir_dout );
macfir_nd