Hi
I am very new to VHDL and in partuclar ModelSim, so of course I have a simple starting exercise to learn from. I want to simulate this RAM model: (thankyou John Aynsley from Doulos) using the testbench that I have pasted under this model. Everything works fine until I assert the OE signal, i.e. OE Byte'(others=>'U')); begin Data 'Z'); if CS = '0' then if OE = '0' then -- Read operation Data
Your testbench is also driving the signal data at the same time that 'RamChip' is. At the time when you assert 'OE' into the RAM, you also need to drive 'data' to all 'Z'. Something like the following...
Kevin Jennings
Thanks for that kevin. That's awesome. David
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