new to fpga

First of all for FPGAs you should start counting LUTs not gates.

A serious problem with questions like these is that it really depends on the quality of the designers that work on the task. Try to google for applications that have many FPGA implementations like AES encryption cores, Java Processors or implementations of legacy processors like 6502 or 8051. You will notice that size and performance vary by a factor of 10 at least. And this is usually not an area/delay tradeoff. In many cases the smaller solution has also the higher performance.

Or read this newsgroup: When the dedicated multipliers in virtex-II were announced there where both complaints that these were slower than multipliers implemented in the regular fabric as well as complaints that it were impossible to implement dsp systems with the clock rate claimed by the manufacturer. These clearly came from designers living in different worlds from each other ;-)

You really should talk to whoever is going to implement the design for estimates.

However, I can give you a first rule of thumb for regular DSP systems (FIR-filters and the like). Assuming that you do not apply any sophisticated transformations to your design like nibble serial operation or the like (which probably you should). The newer architectures from Xilinx and Altera provide you with 18-Bit Multipliers that run around 100Mhz without much effort. Determine how many of these you need and select a chip based on that estimate. Then check wether the internal RAMs are sufficient for you memory architecture (delay lines, coefficients, etc.). You are probably not going to run out of logic ressources for most straigth forward DSP implementations.

Kolja Sulimma

After selecting a manufacturer you should download their free design software. Then do the design and get a fitting FPGA as output of this evaluation process.

Rene