new Lattice FPGAs vs Cyclone and SpartanIII

I am just wandering if any of you have take a look at the Lattice FPGAs. I do like the DSP functions. is out there any serious comparation against SpartanIII and Cyclone?

regards,

paul

Reply to
Paul Sereno
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What special did u find on it?? on the first glance it looks similar to what altera is proving for year as DSP block

Reply to
digari

IMHO, Altera's DSP block is only a multiplier. The MAC block Lattice is proposing is much richer: reg, mult, pipeline reg, accu, reg. On top of it, the IO cell has more regs than any other comparable architecture. Anyone tried to implement DDR333 on Cyclone or S3?

rgrds,

Reply to
Luc Braeckman

Please have a look at:

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and then see where Latice got thier ideas from. But you are correct for the lowcost families Altera (CycloneII) and Xilinx (spartan-3) has chosen Multipliers rather then DSP blocks. Put if you call Alteras DSP block a mulitiplyer you have to say the same about Latice since there are at least on the marketing slides I have seen identical. YMHO Fredrik

Reply to
Fredrik

Reply to
Luc Braeckman

I agree with Luc. The DSP blocks are just great for a low cost FPGA. Stratix have the same or similar but you need to pay for them. Another point that Luc mentioned is the DDR capabilities. There is a dedicated hardware (DLL and input registers) to facilitate the DDR interface without needing to waste LUT on it. I like that as well. Clocking scheme looks good. Great range of freq from analog PLLs. Normal 4 quadrants. It seems the market for the low cost FPGA is getting hot with one good new member. ..

paul

Reply to
Paul Sereno

Have any of you tried Lattice's software for their new -EC parts? How close is it to Xilinx (they share a common heritage)? I'm trying to get a feel for its quality and stability.

Things should be getting interesting when their 90nm -SC parts come out (vs. Stratix-II and Virtex-4), especially with their cool DDR I/O interface. Perhaps Lattice will make a come-back?

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int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
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Reply to
Joseph H Allen

Reply to
Fredrik

Joseph,

I tried the software, and it looks good. As you mentioned, they share a similar GUI, even the EPIC editor is similar. Of course the libraries aren't complete yet, but it gives you a good feeling of the possibilities.

You're right, with the introduction of the 90nm SC parts, I think they can compete with every other high-end FPGA.

Luc ___

Reply to
Luc Braeckman

continuing the discussion about Lattice's DSP block, I found the following interesting article:

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regards,

paul

Reply to
Paul Sereno

The local Lattice FAE gave us the low-down. Looks like a decent set of chips.

One thing we REALLY liked is that if you go with the devices that use an external configuration EPROM (rather than the family with the internal config flash), you can use a standard (read: CHEAP) SPI device, rather than a non-cheap specific config chip.

I've always wondered why Brand A and Brand X continue to use their expensive config parts. Actually, that's not true -- I know why. Seriously, what's the point of using a $10 FPGA when the config EPROM is also $10?

-a

Reply to
Andy Peters

Altera has addressed this problem with the Cyclone family - the configuration devices are quite cheap.

Leon

Reply to
Leon Heller

: The local Lattice FAE gave us the low-down. Looks like a decent set : of chips.

: One thing we REALLY liked is that if you go with the devices that use : an external configuration EPROM (rather than the family with the : internal config flash), you can use a standard (read: CHEAP) SPI : device, rather than a non-cheap specific config chip.

: I've always wondered why Brand A and Brand X continue to use their : expensive config parts. Actually, that's not true -- I know why. : Seriously, what's the point of using a $10 FPGA when the config EPROM : is also $10?

X tries to come up with the XCF Series, also the XCF has still delivery problems.

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Reply to
Uwe Bonnes

As far as I could discover, this is still a propriatary device, and therefore you could not use a standard SPI flash instead. If no competition (read pin/pin compatible replacement) is possible, Altera could keep up the price as high as they want. With standard SPI flash, I have the choice of at least 5 different suppliers, no potentialy delivery problems, and guaranteed lowest price. Thus driving the total solution cost to a minimum.

Luc

Reply to
Luc Braeckman

Still unverified by me, but someone pointed here some time ago that EPCS devices are indeed a standard device produced by ST (M25Px0). Anyway, if that's true, Altera has a quite expensive paint... :D

Ricardo

Reply to
Ricardo

I suppose you could use an SPI flash in conjuction with a cheap up like a PIC (some of those are less than a dollar, and they even have one in a SOT23 package) to undercut the cost of the serial config ROMs.

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

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"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Reply to
Ray Andraka

Just FYI, there is an application note on this very topic that demonstrates how to configure a Xilinx FPGA from an SPI serial Flash using a small CPLD. The application note is written for CoolRunner-II, but practically any Xilinx CPLD will do.

XAPP800: Configuring Xilinx FPGAs with SPI Flash Memories Using CoolRunner-II CPLDs

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While we're on the subject, have you ever wanted to store additional information in the configuration memory (serial numbers, Ethernet MAC IDs, MicroBlaze code) and read it after the FPGA configures? If so, the following application note may be of interest.

XAPP694: Reading User Data from Configuration PROMs

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The two demo designs for the Spartan-3 Starter Kit also demonstrate this capability.

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--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

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--------------------------------- Spartan-3: Make it Your ASIC

PIC (some of those are less than a dollar,

serial config ROMs.

Reply to
Steven K. Knapp

Of course you can, why not building a complete system just to configure the FPGA (sic). The idea of a cheap SPI flash directly connected to the FPGA is very attractive, especially in consumer application where every cent counts.

Regards,

Luc ___ >Just FYI, there is an application note on this very topic that demonstrates

Reply to
Luc Braeckman

Yeah, but this solution still requires another part. Perhaps reasonable if you needed the CPLD for other things, but otherwise it's not a very good solution. Some boards are overstuffed as it is!

I remember using a 9536 to interface a parallel EPROM to XC4000-series parts, but that was ages ago, before the G-dsend known as in-system JTAG-programmable parts ...

Reply to
Andy Peters

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