netlist tricks

Hi,

to everyone who thought about doing calculations with netlists . eg. external pins, internal states are known (from reset state) to figure out the remaining signals, lets say 100% visibility.

Does anybody thought about that?

kind regards, thomas

Reply to
T. Irmen
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What?

Reply to
Matt

Hi Matt,

I mean: You have a board with a few fpga´s running your partinioned design. You record all IO´s into RAM on the fastes clock (how much depends on your RAM size). After a trigger you stop and download the RAM. With this information you step into the netlists, to explore the internal signals. I think every boolean equation could be calculated, so every signal is visible - 100%.

clear? kind regards, thomas

"Matt" schrieb im Newsbeitrag news:L_A0c.91758$4o.116746@attbi_s52...

out

Reply to
T. Irmen

It sounds like you want to somehow feed the contents of this RAM back into a simulation to reproduce all of the design internals?

Reply to
Gabor Szakacs

Yep,

the idea is to record this and use the netlists in the simulation. Is there a way to use edif netlists in modelsim, with usable signal names?

What is the preferred way (performance): record first and then watch

or record and watch on the fly?

thomas

"Gabor Szakacs" schrieb im Newsbeitrag news: snipped-for-privacy@posting.google.com...

RAM

information

every

Reply to
T. Irmen

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