I am using virtes II pro pci card .The card has a pci bridge with a bus linking processor in the bridge to the fpga. The constraints on the processor bus signals were givent by the vendor. My design gives me a negative slack on 2 of the signals on the processor bus. Will this affect the design ? I am doing dma from the fpga to the host RAM along the bus. The transfer rate is low. I was googling for links to read on negative slacks but could not find good ones for a starter. Thanks,
-D
Not knowing what tool you're using that is reporting the slack makes it impossible to be certain but the basic defintion of 'slack is roughly....
'Slack' is the amount of time you have that is measured from when an event 'actually happens' and when it 'must happen' .. The term 'actually happens' can also be taken as being a predicted time for when the event will 'actually happen'.
When something 'must happen' can also be called a 'deadline' so another defintion of slack would be the time from when something 'actually happens' (call this Tact) until the deadline (call this Tdead).
Slack = Tdead - Tact.
Negative slack implies that the 'actually happen' time is later than the 'deadlin' time...in other words it's too late and a timing violation....you have a timing problem that needs some attention.
KJ
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