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need your comments

Hi all, I need to get a feedback from you experts on some of the guidelines I adopted within my project with a Spartan3 FT256:

1) so far only 100 I/O pins out of 173 have been assigned, all the others will be sent to a common connector for future use. In order to handle, in future, all the pins available I decided to build up a PDS large enough for all the Vcc/GND couples. I followed the suggestions of xapp623 and here's what I calculated: Vcco: 14x 0.01uF, 6x 0.1uF, 4x 1uF, 1x 10uF; Vccint: 4x 0.01uF, 2x 0.1uF, 2x 1uF, 1x 10uF; Vccaux: 4x 0.01uF, 2x 0.1uF, 2x 1uF; 2) I'll have to deal with a Blackfin DSP which has very steep rising and falling edges, so I think I'll need termination resistances, or to use DCI, but as far as I'm working with the LVCMOS33 standard, there seem to be no DCI on input pins, what should I do? 3) I'd like to use the same pins of the DSP for both serial configuration and normal serial communication with the FPGA, to accomplish that the DSP_ATA_OUT will be connected to the DIN of the FPGA. This pin is dual-purpose so, after configuration, I'll use it as FPGA_DATA_IN. The CCLK, instead, is a dedicated pin, so I need to redirect, after configuration, the DSP_CLOCK signal from CCLK to the FPGA_SERIAL_CLOCK. What would you suggest me to do, to just connect DSP_CLOCK to both FPGA_SERIAL_CLOCK and CCLK at the same time (considering that during startup the former is Hi-Z, while during normal work the latter will be Hi-Z), or should I place some logic gates to close one path and to open the other, switching with the DONE signal? Thanks, Marco
Reply to
Marco
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Marco, We just designed a board that does just what you've described above. We have a signal going in to CCLK, which is also tied to a GPIO for use after configuration. It's stated in the datasheet that all inputs to CCLK after configuration are ignored, so that's not a problem. However I wouldn't assume that the GPIO is Hi-Z during during configuration. It depends on what you've done with the HSWAP_EN pin. We have that pin tied to GND which gives all of the GPIO weak pullups during configuration. This has not been a problem for us, so having external logic is not necessary. We are using parallel slave config mode. After configuration D0-D7 are used for the normal DSP data bus. Another thing to keep in mind: What is the signal voltage of your DSP? If it's not 2.5V, I would recommend having a look at this app not from Xilinx.

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Hope this helps.

Dale

Reply to
dale.prather

Dale, the signal voltage is 3.3V, so I use the LVCOMS33 standard for the whole I/Os. I also placed 100 Ohm current limiting resistances on TCK, TDI, TMS, CCLK, PROG_B. Then TDO, CCLK, PROG_B and DONE are all pulled up with 10kOhm, should I do the same for INIT_B (that will later be used as GPIO)? Your suggestion helps me with point 3 (thanks so much), do you or others have any comments also on terminations and PDS questions? I'd really appreciate. Marco

Reply to
Marco

Marco, I have Init_B pulled up to 3.3V with a 4.75k resistor, but I'm not using it as a GPIO. I also have Done pulled up with a 330R. The others are not pulled up.

Why are you doing anything with the TMS, TDI, TCK and TDO signals? These signals are for configuring the FPGA through the JTAG port. Are you setting up the FPGA to also be configured by JTAG as a backup plan? Probably not a bad idea, at least for prototypes.

I don't know your background, so I'm sorry if I stated something obvious.

Dale

Reply to
dale.prather

Dale, I thank you for every suggestion, nothing is obvious to me. Yes, I decided to place the JTAG port on the board for both the DSP and the FPGA (one each and not in a chain) in order to have one more feature letting me understand if something is going wrong and how to solve it. What do you think about the PDS? On many other boards they use less different capacitor sizes, say just 0.01uF and 1uF, while I followed the Xapp623 guidelines, mainly because this is my first experience. Then, how did you handle M0-M2 signal? With a switch/jumper to GND or Vcc? Thanks again Marco

Reply to
Marco

I hard wired the mode signals according to the config mode you're using. In your case, serial slave, I believe. You don't need a switch or jumper. JTAG config mode is always available regardless of what you do with the mode pins. Setting them to JTAG mode only disables all other modes, unnecessarily.

As far as the decoupling caps. I think following Xapp623 is overkill. It's a project by project thing, but we're in aerospace in about as noisy an environment as it gets. We use one 0805, 0.1uF, 50V cap per power pin on the FPGA (all rails). We use this approach for every IC on the board, which may also be a little overkill, but it's fairyl inexpensive. In retrospect, to save on board space, I wish I would've use 0402 caps. There's no reason not to, as long as your manufacturer can handle it.

Dale

Reply to
dale.prather

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