Need some assistance with ISE OFFSET constraint.

I am trying to meet an offset timing constraint, but I'm not sure I understand the timing report. What's the deal with the long IOB FF to PAD delay from Tiockp? It seems highly dependent on the DCM clock path prior, so I'm not sure how to improve this...

Thanks,

-Brandon

================================================================================ Timing constraint: COMP "S0_BPLK_OUT" OFFSET = OUT 4 ns AFTER COMP "DSP_CLK" HIGH;

1 item analyzed, 1 timing error detected. Minimum allowable offset is 4.315ns.

-------------------------------------------------------------------------------- Slack: -0.315ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: reg_data_2_1_1 (FF) Destination: S0_BPLK_OUT (PAD) Source Clock: DSP_CLKi rising at 0.000ns Requirement: 4.000ns Data Path Delay: 4.686ns (Levels of Logic = 0) Clock Path Delay: -0.371ns (Levels of Logic = 3) Clock Uncertainty: 0.000ns Timing Improvement Wizard Clock Path: DSP_CLK to reg_data_2_1_1 Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tiopi 0.723 DSP_CLK dsp_clk_ibufg_ins net (fanout=1) 0.798 DSP_CLKibufg Tdcmino -5.744 dsp_clk_dcm_ins net (fanout=1) 0.839 DSP_CLKubi Tgi0o 0.589 dsp_clk_bufg_ins net (fanout=414) 2.424 DSP_CLKi ---------------------------- --------------------------- Total -0.371ns (-4.432ns logic, 4.061ns route)

Data Path: reg_data_2_1_1 to S0_BPLK_OUT Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tiockp 4.686 reg_data_2_1_1 S0_BPLK_OUT_1_OBUF S0_BPLK_OUT ---------------------------- --------------------------- Total 4.686ns (4.686ns logic, 0.000ns route) (100.0% logic, 0.0% route)

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Reply to
Brandon Jasionowski
Loading thread data ...
1) what family and speed grade, 2) what IOB Standard, and 3) what are your expectations and why?

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Reply to
John_H
1) Virtex 2, -4 speed 2) There isn't an IOSTANDARD specified for the IO pins in the project UCF the board vendor supplied me with. What does this default to? Do I need to contact the vendor to ask them what the board can support? 3) I was told by the vendor this number would be appr> 1) what family and speed grade,

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Reply to
Brandon Jasionowski

For LVTTL (12mA) - the default for no IOB - the Tiockp is 2144 ps according to the speedprint utility. An extra 2626 ps is needed for the "slow" outputs for a total Tiockp of 4870 ps which is closer to your 4689 value but not precise. Specifying FAST constraints on the outputs should help out significantly.

Take a look at the IOB Properties in the ISE GUI's Design Overview section. There you'll have a list of the I/Os, the standards, drive strengths, and slew rates specified. Tweak those values with Xilinx User Constraints and you should get your timing. The different parameters you see - values other than LVTTL, 12 mA, slow - or the version of tools you're running should be responsible for the difference I noted above.

- John_H

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Reply to
John_H

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