I have a number of Dual-Port Rams and FIFOs that I've implemented with Quartus II 6.0 sp#1, targeting a Stratix II device.
When I simulate with my test bench in the "functional" world, everything acts as expected.
When I compile the .vho/.sdo files and run against a slightly modified test bench (differences in output file names and the test bench calling out the VITAL version of the FPGA implementation), it appears that there is an additional register delay that has been introduced into the Dual-Port/Fifo implementations.
Is this normal? Or do I need to make some type of adjustment for this behavior? I don't quite know how to explain/justify the differences at this point.
I had specified in the Megawizard setup for each of the memory types, that the output was registered -- I'd think that the functional model would work the same as the gate level implementation of the Fifos/Rams.