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Need help with using inout (bi-dir) in VHDL for Xilinx FPGA

Hi All -

I am trying to use bi-directional I/O pin in VHDL (inout). When I run it through the Xilinx ISE, in the Pad report it converts the inout pin as output. Is there any sample example/code which I can try to make sure I am not writing something incorrect. Thanks.

- Sunil

Reply to
sg
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Are you sure you use the pin for internal logic ?

Reply to
A Beaujean

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