Hi All,
I am working on SD Card IP Core for Altera FPGA which has DDR interface.Input and Output Timing requirements for SD Card is given below
tISUddr (Input Setup Time) = 2.5ns, tIHddr (Input Hold Time) = 2.5ns, tODLYddr_max(Output tCO Maximum) = 7ns, tODLYddr_min(Output tCO Minimum) = 1.5ns, tPP(Clock Period) = 20ns
I have given timing constraint to Input/Output port in following manner.
//Clock Constraint
create_clock -name CLK -period 20ns [get_ports{CLK}]
//Input Delay Constraint
set_input_delay -clock { CLK } -max -add_delay $tODLYddr_max [get_ports {SD_DATA*}] set_input_delay -clock { CLK } -min -add_delay -$tODLYddr_min [get_ports {SD_DATA*}]
set_input_delay -clock { CLK } -clock_fall -max -add_delay $tODLYddr_max [get_ports {SD_DATA*}] set_input_delay -clock { CLK } -clock_fall -min -add_delay -$tODLYddr_min [get_ports {SD_DATA*}]
//Set False path between rising edge of CLK to falling edge of CLK
set_false_path -setup -rise_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}] set_false_path -setup -fall_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}] set_false_path -hold -fall_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}] set_false_path -hold -rise_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}]
//Output Delay Constraint
set_input_delay -clock { CLK } -max -add_delay $tISUddr [get_ports {SD_DATA*}] set_input_delay -clock { CLK } -min -add_delay -$tIHddr [get_ports {SD_DATA*}]
set_input_delay -clock { CLK } -clock_fall -max -add_delay $tISUddr [get_ports {SD_DATA*}] set_input_delay -clock { CLK } -clock_fall -min -add_delay -$tIHddr [get_ports {SD_DATA*}]
//Set False path between rising edge of CLK to falling edge of CLK
set_false_path -setup -rise_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}] set_false_path -setup -fall_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}] set_false_path -hold -fall_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}] set_false_path -hold -rise_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}]
//ALTDDIO BIDIR Megafunction Instance
alt_ddio_bidir inst ( //DDIO Out Port
outclock (CLK), datain_h (data_out_h), datain_l (data_out_l),
oe (dir),
//DDIO In Port
inclock (CLK), dataout_h (data_in_h), dataou_l (data_in_l) );
Here CLK is used to generate data_out_h and data_out_l signals during write operation and the same CLK is used to capture data_in_h and data_in_l signals.Same CLK is given to SD Card also.
Is these timing constraints are correct?
I refer some Altera's document in which center align or phase shifted clock is used to provide input/output delay constraint.
Is it mandatory to use different launch and latch clock in case of DDR data interface?
Thanks in advance.
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