need desperate help!

Did you simulate the pure Verilog code or the back-annotated code (i.e. after synthesis)? You know, not every formally valid code will be correctly synthesized. I don't know Verilog and so I cannot give comments to your code. So you should check whether you described your problem using the right coding conventions.

Also check whether you got some timing problems.

Regards, Mario

Did you apply timing constraints to the design ... does your design meet the timing constraints. As a minimum you should have three bassic constraints applied ... FFS to FFS FFS to PADs PADs to FFS

Mike

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IO_control(ALE,NWR,NRD,DIR,DA,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,clk);

Hi Filippo,

I assume the clk signal in your code is the AVR clock. You should implement the interface asynchronously and when you have the data in the FPGA synchronize it to whatever clock you have there. This is an excerpt from the ATmega162L datasheet:

"Note that the XMEM interface is asynchronous and that the waveforms in the figures below are related to the internal system clock. The skew between the internal and external clock (XTAL1) is not guaranteed (it varies between devices, temperature, and supply voltage). Consequently, the XMEM interface is not suited for synchronous operation."

Regards,

-- Georgi

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IO_control(ALE,NWR,NRD,DIR,DA,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,clk);

Here's one suspect:

You can drive a Z for synthesis, but you can't read one. Consider adding an output enable signal.

-- Mike Treseler

Did you perform both pre- and post-route simulations? What does your test bench actually do? Is it a real bus-functional model of your microcontroller? Or are you just setting and clearing signals in some arbitrary fashion? I would imagine that this is the root of your problem -- your simulation is bogus. As they say: garbage in, garbage out?

What about your timing constraints?

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^^^^^^^^^^^ This initialization is illegal, or at least ignored by a synthesis tool. Use an external reset to actually initialize these registers.

Ummmmm...why not declare the SEL, TYPEFIL, AMPLIF and DIVFRQ outputs as regs and not bother with this silly assign? Also: explicitly declare whether your module outputs are wires or regs. It's a good style habit.

Umm, another style issue. Use more than one always statement for the above. You have three separate registers; put 'em in their own always blocks.

Also: are ALE, NRD, NWR, DA all synchronous to your clock?

Remember that ALE is a latch enable -- are you sure that your address is actually valid when the latch enable is active and goes away?

reg [7:0] TYPEFIL_REG=uno; You can initialize when targeting to synthesis (only for verification). Use reset instead. if(posedge clock or negedge reset_n) begin if(~reset_n) .... else ..

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reg [7:0] TYPEFIL_REG=uno; You can initialize when targeting to synthesis (only for verification). Use reset instead. if(posedge clock or negedge reset_n) begin if(~reset_n) .... else ..

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I made a lot of changes (like the reset) , i'll post the new source soon!

Teacher told us not to do an asynchronous interface , 'cause it won't work ...

maybe he's just a crazy man... but a week ago it was asynchronous and didn't work too

both simulations were succesful

this has changed

humm , i'll think about this

I made a lot of changes:

- split IO_control in two modules : an io buffer (iobuf) and the contoller (IO_Async)

- now it's totally asynchronous

- no more extra reg

- tried to split the big always in many little ones

but now it doesn't work neither with modelsim, post place & route sim results aren't nice. The problem seems to be somewhere between iobuf and IO_Async because when i try to write an address in ADDR it never arrives ? The funny thing is that both modules work fine alone..

here's the code:

------------------------------------------------------------------------------ module IO_Async(ALE,NWR,NRD,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,rst,ibuf,obuf);

input ALE;

input NWR;

input NRD;

input [7:0] MIN;

input [7:0] MAX;

input [7:0] ibuf;

output [7:0] obuf;

output [7:0] SEL;

output [7:0] TYPEFIL;

output [7:0] AMPLIF;

output [7:0] DIVFRQ;

output rst;

reg [7:0] ADDR;

reg [7:0] obuf;

reg [7:0] SEL;

reg [7:0] TYPEFIL;

reg [7:0] AMPLIF;

reg [7:0] DIVFRQ;

reg rst;

// ciclo scrittura ADDR

always @(posedge ALE)

ADDR

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What is dir connected to? Also, I think you don't need a tristate bus for ibuf.

-- Georgi

this are the time diagrams i got:

WRITING CICLE

ALE +--+ | | ---------+ +-------------------

NWR -----------------+ +----------- | | +--+

DA ----\ /-----\ /------\ /------- xxx |adress | data | xxxxxxx ----/ \-----/ \------/ \-------

Now it works (modelsim) i had to split the iobuff in two buffers: one for ibuf and one for obuf. I know it seems crazy , but just "assign ibuf= da;" didn' t work i had to make a tristate buff to make it work .

I hope thursday it will work on the real FPGA ^_^

My point was that if you don't have a reset, the initialize will fool you.

-a