Hi everyone, I have a few doubts that are not being addressed in fpga groups(at least i could not find the one ) though it is very common in DSP design using FPGAs.
- In many a communication receiver systems a resampler (NCO based) is required. The output of the resampler is fed to other logics. Can NCO output be used to drive the portion of the design ? as is sayed that in FPGA clock derived from (combinational/sequential) logics should be avoided and whenever a rate change is required use enable signal instead. But this approach requires the whole design to be run at the highest clock consuming much more power.What could be the power efficent method of doing the same. Most common example is a CIC filter used for large rate change (Not by integer factor but rather rate change is driven by a NCO) where input is at much higher rate while the output is at lower rate.
- If at all NCO is used for clocking the design that is required to run at much slower speed what care should be the taken for NCO master clock driving NCO , to NCO output clock ? (I feel higher the ratio lower the jitter will be).
- Can NCO clock be further used to drive a DCM to produce a high freq clock that can be used for serial MAC fir (for efficient fpga fabric usage.)
regards. rajeev shukla.