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Name this pipelining technique

Hi,

I vaguely recall reading papers that described an automated pipelining technique that could take an existing synchronous design and turn it into a N-way hyperthreaded design by replacing all the flip flops with N chained flip flops.

I'd like to look at those papers again, but I can't remember what it was called, and my google-fu is weak.

Any ideas?

Thanks, Allan

Reply to
Allan Herriman
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I think "C-Slow retiming" is the academic term for the transformation.

The earliest moniker I've heard as applied to a processor is "barrel processor" [CDC], with something like "N-way sequential multithreaded" being the modern terminology.

IIRC, Tobias at edaptix had written some articles about his automated implementation of the technique on the late Programmable Planet website, see:

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-Brian

Reply to
brimdavis

Perhaps PicoPIPE as used(patented) by Archronix?

Hans

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Reply to
HT-Lab

C-Slow it was. Thanks very much.

Regards, Allan

Reply to
Allan Herriman

I've seen it termed 'System Hyper Pipelining'.

Reply to
Mike Field

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