my Spartan-4 wishlist

I keep wondering if there's a market for a few "unbalanced" devices, like something with a ton of gates but in a tqfp-64 package. Or BGA packages that only use the two outer rows for signals, for simpler board routing.

Likewise, I'd like to see the occasional MCU with a ton of ram and a little flash, rather than the other way as it usually is. Every once in a while I need a smart buffer chip :-(

"Antti" schrieb im Newsbeitrag news: snipped-for-privacy@s19g2000prg.googlegroups.com...

Hi Antti,

I've the same wishes, some additional i/O & memory cores would be nice:

7) Ethernet MAC + PHY

9) some analog stuff (ADC, temp sensor, system supervisor)

S4 would be a serious competitor to 32bit microcontrollers, if some of their standard peripherals are included in low price FPGA's.

MIKE

oh yes, TQFP48 0.5mm pitch FPGA running from single voltage! defenetly, but hey thats wish for new Lattice device ;)

BTW, Actel QFN132 3 row QFN 0.5mm pitch CAN be used on

Antti

You forget a standard ARM core, some internal flash (say 32KB to

I also like the large logic core, small package idea. And a builtin optional linear regulator for those pesky 2.5V and 1.2V would be really nice. Add some builtin eeprom for the bitstream (like Spartan-3 AN).

Supposedly Spartan4 will have RocketIOs/GTPs. Or at least there will be a flavour that will have them, so maybe PCIe and SGMII for Gigabit Ethernet?

To me this sounds an awful lot like "We need something like the Lattice ECP2/M!", just like the Spartan3-AN sounds a lot like "We need something like the Lattice XP/XP2!". Lattice must've struck a nerve with those two families, they found their niche of devices Xilinx doesn't really cover (yet)...

BTW, ECP3 is on its way, but supposedly will be not much more than a die shrink of the ECP2.

cu, Sean

I have seen more often need for a huge package and very little logic. Nowadays I have seen that at networking side many designs are becoming I/O limited and the pinouts are more and more complex to do because of all restrictions what can be in what FPGA bank etc.

Hopefully serial interfaces will help in this problem (high speed serial interfaces to memories etc.). But this on the other hand needs also low cost FPGAs with decent amount of tranceivers.

--Kim

In article , DJ Delorie writes: |> |> I keep wondering if there's a market for a few "unbalanced" devices, |> like something with a ton of gates but in a tqfp-64 package.

I bet there is, although probably not a high numbers market -- but anyone dealing with repairing long-gone legacy devices would love such beasts, especially when they come with a separate V_I/O input where one could adjust the logic level to stone-age (5V, 3.3V) -- heck, make at least two voltage domains for easy interfacing -- without the need for external drivers and level shifters.

And don't forget the internal configuration PROM.

Ok, make that thing reasonably priced and you probably have an ASIC killer for modest-run "single chip plus some little discrete" stuff, like e.g. the C64DTV (IIRC 250.000 units were produced). Rainer (practicing geriatronician)

well, Xilinx already own ARM IP-Core license, when Xilinx purchased Triscend they also got the IP licenses ownded by Triscend what included also ARM.

so it is possible that the ARM core see new life in Spartan-4, Xilinx has no extra royalty to pay

Antti

Hey, I'd be happy with pretty much *any* FPGA in a small leaded package, even a 100 pin TQFP. I am doing a current job with the Lattice XP family because it is the *only* FPGA available in a 100 pin QFP. They have exactly one size, the 3000 LUT part which is the smallest in the family. Fortunately there is little chance I will need a larger part. But on the other hand, I won't be able to consider anything fancy for this project because of this limitation. Of course, I could consider a no lead package such as a BGA, but for the most part they are much more expensive, as much as anything, because they have lots more pins.

I think there is an Atmel ARM part which has a huge amount of RAM although I want to say the flash is external, but it might be a dual die approach with both in the same package. It is one of their older parts and I expect it will only run at 33 MHz.

I have not looked very hard at the 132 pin QFN package. But at 0.5 mm pin pitch, how exactly do you route signals from the middle row out? I guess the pins are actually 1.5 mm pitch on each row for 0.5 mm considering all three rows? One of the problems I have using 0.65 mm pitch QFPs is that I can't route between the pins. That is a real PITA. I sometimes think I would be better off with a wider pitch part, but I'm not sure I can fit them on the board... :^(

I thought you could get all that in an MCU? At that point do you even need the FPGA anymore???

After I had presented to the customer my approach using an FPGA do handle the data path for a simple board which had some standard and non standard interfaces, I found out about an ADI part which is a DSP combined with a high resolution Codec. I didn't look at it really hard, but at first glance, it looks like it could have been as good of a solution and a bit cheaper than the FPGA + codec. I will say I prefer writing VHDL to coding DSPs though. The toolsets tend to be cheaper too.

But I have to say the DSP approach looks pretty good.

There are plenty of Spartans in QFP packages, as well as other vendors...

The MCUs I'm working with are 20MHz, 24k flash and 2k ram. I think it would be interesting to see one with 2k flash and 24k ram, for example.

Yes, anything is possible. I might even win the Powerball... no, I don't buy tickets...

So far, Xilinx has given no indication that they bought Triscend for any reason other than to keep ARM out of the FPGA market. Just like so many other companies that Xilinx bought and deleted, the purpose seems to have been to bury the technology rather than to develop it.

Xilinx seems to have a strong opinion that CPU hard cores do not mesh well with FPGAs as it creates too many combinations of RAM, FPGA size and package so that the number of parts blooms to unmanageable numbers. But then Xilinx has a history of making a firm stand on a point and later reversing themselves when *they* think conditions are different. Meanwhile other companies eat their lunch for a bit while they are still making their stand. Embedded memory is one example. Xilinx was one of the last companies to add that to the FPGA. Later the integrated hard logic block was another reversal. I wonder if their line in the sand against Flash FPGAs will be another soon to happen reversal. When the focus on getting the most logic on a die for the lowest price was the main FPGA goal, the anti-Flash opinion sounded good. But I think the density is high enough now that there are tons of applications that will benefit from having the Flash integrated on the die even if there is a die size penalty due to the lagging process technology. Rather like the way that Intel and AMD can't figure out what to do with all the transistors on a die, so they are adding more and more copies of the CPUs, at some point FPGAs will have more than enough LUTs for most apps and other features will become the main selection criteria.

It may not be the Spartan iv, but sometime soon, there will be a combo chip with a right sized FPGA, various peripherals (ones that make sense as a hard core rather than a soft one) and on die Flash memory, both as configuration and program storage for an integrated CPU. Isn't it ST Micro that has the Spear which is an ARM with bells and whistles including a metal programmable gate array? That is just one step away from having an on die FPGA... I would be willing to bet the only thing that stopped them from using an FPGA instead of a metal programmed part was patents... you know, the ones that Triscend had and now are buried in the vaults at Xilinx. I can see a guy pushing a dolly into an endless warehouse as the camera pulls back to show the mountains of buried IP...

Maybe Xilinx was concerned that ARM might prove them wrong?!!

its 0.5mm pitch. middle row pins can not be used on 2 layer PCB only outer and inner row. my application did not need much IO so that was sufficient

Antti

I guess your first statement above that the part "CAN be used" on a 2 layer board means, there is no power or essential control signals on the middle row? So I guess it can be used if you don't mind losing a huge percentage of the I/O?

right there think is 1 JTAG pin in middle row, this can route out via I/O similarly all VCC/IO in middle row can be routed as needed.

Antti

Well, the FPGA usually handles the fast stuff. In most devices which use an FPGA you'll find an MCU as well. So why not embed the MCU + flash +sram inside the FPGA. Sure there is Microblaze and Nios but they cost a lot of logic real-estate and have no internal flash.

Here's mine :

• Easy one :

- Schmitt trigger on the TCK line

• New packages to make prototyping easier and to make the chips easier to use on simpler boards that are less expensive, would translate into costs saving for small / simple systems, and possibly more sales from Xilinx ! Examples :

- Self-centering BGA : put a through-hole pin in each of the corners of the BGA, the PCB designer makes 4 holes on the PCB, and the part now can be placed by a drunk intern, instead of a megabuck BGA placing robot. No, strike that, make it only 3 holes, so you can't put it the wrong way in.

- PQ208 : put thermal pad below connected to GND, remove all GND pins from package ; put other smaller "thermal pads" for the power supplies and get rid of the supply pins, you get 50 more IO on the package.

- BGA usable on a 4-layer board with standard specs (6/6 track and standard holes), instead of 6-layer with super small holes : Solution 1 : remove pins in a cross pattern for escaping with much less vias Solution 2 : Two exterior rows of pins @ 1mm pitch or even 0.8mm pitch, and all internal pins at 1.27mm pitch, to allow vias between the pins even on a cheap PCB process Interior pins :

• A bit more difficult :

- FPGAs shouldn't have input-only pins... the spartan-3E is a bit annoying for this... I know it's a compromise with the IOBs space on die, then a better solution would be a simpler IOB, supporting less features (like only LVCMOS output from the bank's voltage, not all the IOStandards) but please get rid of those input-only pins - If you can't get rid of the input-only pins, on the BGA package put them all in the internal balls close to the chip's center so if the designer doesn't need them he can forget them and save on layers... - more decoupling caps inside the package

• Other :

Hard SDRAM controller (or DDR) core in the chip and stacked SDRAM chip in the package, or multi chip module... you get the idea ;) ARM core

Hey it was supposed to be a wishlist right ? In all of those if I just ge a more noise-tolerant TCK input I'll be happy.