My design to big for the FPGA or not?

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When I try to generate a programming file for my FPGA project I get the
following error:

ERROR:Place:419 - The design contains 4 BRAM components that are configured

   512x36 BRAMs and 9 multiplier components. The multiplier site adjacent to

   location of a 512x36 BRAM component must remain free because of ressource

   sharing. Therefore a device  must have at least 13 multiplier sites for

   design to fit. The currently chosen device has only 12 multiplier sites.
Phase 1.1 (Checksum:98d993) REAL time: 3 secs

I use XILINX ISE 6.3.03i. Is there a way to make my design fit inside the
FPGA without reducing the number of multipliers?

Re: My design to big for the FPGA or not?
You can make the design fit.

Change your BlockRAMs to use x18 width instead of x36.  The multipliers
can share the resources with a BlockRAM unless the BlockRAM uses the
wide 36-bit bus.  Since you're only using 4 BlockRAMs, it would be easy
from a resource perspective to use half of 8 BlockRAMs at 18-bit width
to give you the same memory sizes you have now.  You may be able to
reoptimize for 18-bit width and use just 4 of the BlockRAM and avoid the
troubles altogether.

Another thought might be to access the BlockRAMs at twice the base clock
speed to provide 36-bit operation over 2 18-bit cycles making it look to
the system like it's a 36-bit BlockRAM at the normal clock rate.  This
approach is more complex but often the BlockRAMs aren't pushed to their
maximum speed and time-multiplexing produces cleaner resource usage.

Casio wrote:
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Re: My design to big for the FPGA or not?
Thank you very much, it solved my problem. I had a RAM entity that was 50
bits wide and a total of 64 words. Now I split the 50-bit words into 18, 18
and 14 bits.

Thanks :-)

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