When I try to generate a programming file for my FPGA project I get the following error:
ERROR:Place:419 - The design contains 4 BRAM components that are configured as
512x36 BRAMs and 9 multiplier components. The multiplier site adjacent to thelocation of a 512x36 BRAM component must remain free because of ressource
sharing. Therefore a device must have at least 13 multiplier sites for this
design to fit. The currently chosen device has only 12 multiplier sites. Phase 1.1 (Checksum:98d993) REAL time: 3 secs
I use XILINX ISE 6.3.03i. Is there a way to make my design fit inside the FPGA without reducing the number of multipliers?