Here is my VHDL library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUX42 is port ( dIn_0 : in STD_LOGIC_VECTOR (15 downto 0); dIn_1 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_2 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_3 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_4 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_5 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_6 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_7 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_8 : in STD_LOGIC_VECTOR (15 downto 0); dIn_9 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_10 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_11 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_12 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_13 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_14 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_15 : in STD_LOGIC_VECTOR (15 downto 0); dIn_16 : in STD_LOGIC_VECTOR (15 downto 0); dIn_17 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_18 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_19 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_20 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_21 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_22 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_23 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_24 : in STD_LOGIC_VECTOR (15 downto 0); dIn_25 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_26 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_27 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_28 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_29 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_30 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_31 : in STD_LOGIC_VECTOR (15 downto 0); dIn_32 : in STD_LOGIC_VECTOR (15 downto 0); dIn_33 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_34 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_35 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_36 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_37 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_38 : in STD_LOGIC_VECTOR (15 downto 0); dIn_39 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_40 : in STD_LOGIC_VECTOR (15 downto 0);
dIn_41 : in STD_LOGIC_VECTOR (15 downto 0); sel_0 : in STD_LOGIC; -- select mux input sel_1 : in STD_LOGIC; -- select mux input
sel_2 : in STD_LOGIC; -- select mux input sel_3 : in STD_LOGIC; -- select mux input
sel_4 : in STD_LOGIC; -- select mux input sel_5 : in STD_LOGIC; -- select mux input
dOut : out STD_LOGIC_VECTOR (15 downto 0)
); end MUX42; --}} End of automatically maintained section architecture MUX42 of MUX42 is signal adr: std_logic_vector(5 downto 0);
begin adr <= sel_5 & sel_4 & sel_3 & sel_2 & sel_1 & sel_0; with adr select dOut<= dIn_0 when "000000", dIn_1 when "000001", dIn_2 when "000010", dIn_3 when "000011", dIn_4 when "000100", dIn_5 when "000101", dIn_6 when "000110", dIn_7 when "000111", dIn_8 when "001000", dIn_9 when "001001", dIn_10 when "001010", dIn_11 when "001011", dIn_12 when "001100", dIn_13 when "001101", dIn_14 when "001110", dIn_15 when "001111", dIn_16 when "010000", dIn_17 when "010001", dIn_18 when "010010", dIn_19 when "010011", dIn_20 when "010100", dIn_21 when "010101", dIn_22 when "010110", dIn_23 when "010111", dIn_24 when "011000", dIn_25 when "011001", dIn_26 when "011010", dIn_27 when "011011", dIn_28 when "011100", dIn_29 when "011101", dIn_30 when "011110", dIn_31 when "011111", dIn_32 when "100000", dIn_33 when "100001", dIn_34 when "100010", dIn_35 when "100011", dIn_36 when "100100", dIn_37 when "100101", dIn_38 when "100110", dIn_39 when "100111", dIn_40 when "101000", dIn_41 when