multisource on signal in XPS

basically we are using ddr ram and the multi source error is coming for the signal sys_clk in dcm module.......

thanx again SAVS.

Not much to tell from what you expose, but...

Maybe you are calling sys_clk the signal coming from outside into DCM clock input, and also the signal coming out of the DCM and beeng fed back to it. These should be two different signals.

This is only a guess from all the information you do not give us.

Regards,

Zara

thanx for the reply .... this is my ports table ..... if it helps ....

Port Name Net Name Polarity ________ __________ _________

CLKON dcm_clk_s I CLK0 sys_clk_s O CLK90 clk_90_s O CLK180 sys_clk_n_s O CLK270 clk_90_n_s O CLKFB sys_clk_s I

thanx again.... SAVS.

Zara wrote:

That listing seems OK. Maybe the external clock port to your system has been connected to sys_clk_s instead of dcm_clk_s,as it should.

Regards,

Zara

You mentioned that you were trying to implement a muticore processor. I am not sure what you meant by it, but you could have instantiated two DCM by mistake...

You might want to post your MHS file if you want to get more help .

/Mikhail

here is the mhs file ....... though in this there is only one instance of microblaze .... still not working ....

PARAMETER VERSION = 2.1.0

PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Addr_pin = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Addr, VEC = [0:12], DIR = OUT PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_BankAddr_pin = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_BankAddr, VEC = [0:1], DIR = OUT PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CASn_pin = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CASn, DIR = OUT PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CKE_pin = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CKE, DIR = OUT PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CSn_pin = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CSn, DIR = OUT PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_RASn_pin = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_RASn, DIR = OUT PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_WEn_pin = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_WEn, DIR = OUT PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DM_pin = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DM, VEC = [0:1], DIR = OUT PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DQS_pin = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DQS, VEC = [0:1], DIR = INOUT PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DQ_pin = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DQ, VEC = [0:15], DIR = INOUT PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Clk_pin = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Clk, DIR = OUT PORT fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Clkn_pin = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Clkn, DIR = OUT PORT fpga_0_HYB25D256800AT_DDR_CLK_FB = ddr_feedback_s, DIR = IN PORT sys_clk_pin = dcm_clk_s, DIR = IN PORT sys_rst_pin = sys_rst_s, DIR = IN PORT OPB_Clk = sys_clk_s, DIR = IN PORT OPB_Clk_n = sys_clk_n_s, DIR = IN

BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 4.00.a PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_NUMBER_OF_PC_BRK = 2 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb PORT CLK = sys_clk_s PORT DBG_CAPTURE = DBG_CAPTURE_s PORT DBG_CLK = DBG_CLK_s PORT DBG_REG_EN = DBG_REG_EN_s PORT DBG_TDI = DBG_TDI_s PORT DBG_TDO = DBG_TDO_s PORT DBG_UPDATE = DBG_UPDATE_s END

BEGIN opb_v20 PARAMETER INSTANCE = mb_opb PARAMETER HW_VER = 1.10.c PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_BASEADDR = 0x31000000 PARAMETER C_HIGHADDR = 0x3100ffff PORT SYS_Rst = sys_rst_s PORT OPB_Clk = sys_clk_s END

BEGIN opb_mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.00.a PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x41400000 PARAMETER C_HIGHADDR = 0x4140ffff BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT DBG_CAPTURE_0 = DBG_CAPTURE_s PORT DBG_CLK_0 = DBG_CLK_s PORT DBG_REG_EN_0 = DBG_REG_EN_s PORT DBG_TDI_0 = DBG_TDI_s PORT DBG_TDO_0 = DBG_TDO_s PORT DBG_UPDATE_0 = DBG_UPDATE_s END

BEGIN opb_ddr PARAMETER INSTANCE = Infineon_DDR_HYB25D256800AT_7 PARAMETER HW_VER = 1.10.a PARAMETER C_DDR_DWIDTH = 16 PARAMETER C_OPB_CLK_PERIOD_PS = 10000 PARAMETER C_INCLUDE_BURST_SUPPORT = 1 PARAMETER C_REG_DIMM = 1 PARAMETER C_DDR_TMRD = 20000 PARAMETER C_DDR_TWR = 20000 PARAMETER C_DDR_TRAS = 60000 PARAMETER C_DDR_TRC = 90000 PARAMETER C_DDR_TRFC = 100000 PARAMETER C_DDR_TRCD = 30000 PARAMETER C_DDR_TRRD = 20000 PARAMETER C_DDR_TRP = 30000 PARAMETER C_DDR_TREFC = 70300000 PARAMETER C_DDR_AWIDTH = 13 PARAMETER C_DDR_COL_AWIDTH = 10 PARAMETER C_DDR_BANK_AWIDTH = 2 PARAMETER C_NUM_BANKS_MEM = 1 PARAMETER C_NUM_CLK_PAIRS = 1 PARAMETER C_MEM0_BASEADDR = 0x00000000 PARAMETER C_MEM0_HIGHADDR = 0x003fffff BUS_INTERFACE SOPB = ddrram_opb PORT OPB_Clk = sys_clk_s PORT DDR_Addr = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Addr PORT DDR_BankAddr = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_BankAddr PORT DDR_CASn = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CASn PORT DDR_CKE = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CKE PORT DDR_CSn = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_CSn PORT DDR_RASn = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_RASn PORT DDR_WEn = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_WEn PORT DDR_DM = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DM PORT DDR_DQS = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DQS PORT DDR_DQ = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_DQ PORT DDR_Clk = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Clk PORT DDR_Clkn = fpga_0_Infineon_DDR_HYB25D256800AT_7_DDR_Clkn PORT Clk90_in = clk_90_s PORT Clk90_in_n = clk_90_n_s PORT OPB_Clk_n = sys_clk_n_s PORT DDR_Clk90_in = ddr_clk_90_s PORT DDR_Clk90_in_n = ddr_clk_90_n_s END

BEGIN dcm_module PARAMETER INSTANCE = dcm_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLK180_BUF = TRUE PARAMETER C_CLK270_BUF = TRUE PARAMETER C_CLK90_BUF = TRUE PARAMETER C_CLKIN_PERIOD = 10.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_EXT_RESET_HIGH = 1 PORT CLKIN = sys_clk_s PORT CLK0 = dcm_clk_s PORT CLK90 = clk_90_s PORT CLK180 = dcm_clk_n_s PORT CLK270 = clk_90_n_s PORT CLKFB = dcm_1_FB PORT RST = net_gnd PORT LOCKED = dcm_0_lock END

BEGIN bram_block PARAMETER INSTANCE = tag_bram PARAMETER HW_VER = 1.00.a PARAMETER C_PORT_AWIDTH = 32 PARAMETER C_PORT_DWIDTH = 32 PARAMETER C_MEMSIZE = 2048 BUS_INTERFACE PORTA = tag_connector END

BEGIN bram_block PARAMETER INSTANCE = cac_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = cac_connector END

BEGIN opb_bram_if_cntlr PARAMETER INSTANCE = opb_tag_bram_cntlr PARAMETER HW_VER = 1.00.a PARAMETER c_baseaddr = 0x00000000 PARAMETER c_highaddr = 0x0000ffff BUS_INTERFACE SOPB = tag_opb BUS_INTERFACE PORTA = tag_connector PORT opb_clk = sys_clk_s END

BEGIN opb_bram_if_cntlr PARAMETER INSTANCE = opb_cac_bram_cntlr PARAMETER HW_VER = 1.00.a PARAMETER c_baseaddr = 0x00000000 PARAMETER c_highaddr = 0x0000ffff BUS_INTERFACE SOPB = cac_opb BUS_INTERFACE PORTA = cac_connector PORT opb_clk = sys_clk_s END

BEGIN opb_v20 PARAMETER INSTANCE = tag_opb PARAMETER HW_VER = 1.10.c PARAMETER C_BASEADDR = 0x42c00000 PARAMETER C_HIGHADDR = 0x42c0ffff PORT OPB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_s END

BEGIN opb_v20 PARAMETER INSTANCE = cac_opb PARAMETER HW_VER = 1.10.c PARAMETER C_BASEADDR = 0x42c40000 PARAMETER C_HIGHADDR = 0x42c4ffff PORT OPB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_s END

BEGIN opb_v20 PARAMETER INSTANCE = ddrram_opb PARAMETER HW_VER = 1.10.c PARAMETER C_BASEADDR = 0x42c20000 PARAMETER C_HIGHADDR = 0x42c2ffff PORT OPB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_s END

BEGIN cntrl_cache_masters PARAMETER INSTANCE = cntrl_cache_masters_0 PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x76000000 PARAMETER C_HIGHADDR = 0x7600ffff BUS_INTERFACE CAC_OPB = cac_opb BUS_INTERFACE TAG_OPB = tag_opb BUS_INTERFACE DDRRAM_OPB = ddrram_opb BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s END

BEGIN dcm_module PARAMETER INSTANCE = dcm_1 PARAMETER HW_VER = 1.00.a PORT RST = dcm_0_lock PORT CLKIN = ddr_feedback_s PORT CLKFB = dcm_1_FB PORT CLK0 = dcm_1_FB PORT CLK90 = ddr_clk_90_s PORT CLK270 = ddr_clk_90_n_s PORT LOCKED = dcm_1_lock END

You inverted CLKIN and CLK0

Let's have a look...

There it is:

"sys_clk_pin" is the external pin where the clock comes into the fpga. You tell EDK to use the internal signal "dcm_clk_s" for this clock, i.e. to drive the internal signal "dcm_clk_s" from the pin "sys_clk_pin".

... and here you connect the OUTPUT of the DCM (CLKIN is the input, as the name suggests, CLK0 is an output) to the same signal as above. So "dcm_clk_s" is driven both by the DCM and by the external clock that comes into the FPGA => multisource signal. You need to swap "sys_clk_s" and "dcm_clk_s" here.

This is just what Zara suggested.

cu, Sean

thanx a lot ppl .......

SAVS.