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multiply by 1.5 in xilinx Virtex2 FPGA

Hi,

Is it possible to generate multiply by 1.5 clock in xilinx virtex2 fpgas using DCMs?

Regards Ganesan

Reply to
Ganesan
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using DCMs?

It sure is!

The CLKFX_MULTIPLY/CLKFX_DIVIDE ratio is chosen as 3/2. As long as the input is at least 1 MHz and the output is within the Max frequency spec, you're set. Check the Functional data sheet for a description of the DFS mode and the DC & Switching data sheet for the DCM's DFS mode input and output frequency constraints.

Reply to
John_H

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