I have been tasked with trying to implement a FFT algorithm in a FPGA/DSP architecture. The algorithm would be a N point FFT with 1000 frequency bins. Each frequency bin would require a multiply, by the constant e^jx, and then accumulate every 1 microsecond. This turns out to be 1000 multiply accumulates happening in parallel every 1 microsecond. Does anyone have experience doing something similar in an FPGA/DSP and can they point me in the right direction as far as choosing a FPGA/DSP development board? Any help would be appreciated.
- posted
18 years ago