multiple clocking in FPGA

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Hello all,

We are developing some design in FPGA XC2V2000, did not decide
the speed grade yet. The design is simple, except the fact that it has
many clocks (more than 16), as a result of many interfaces, some of
them  NCO-generated, some are slow, and some are fast.
So, i have two questions.

Question #1:
Say, i have a number of interfaces, which give me nothing but clock
and serial data. The corresponding clock is used for only one purpose:
writing this serial data into FIFO; that's all.
Can i put this clock on a global I/O (not global clock) pin and simply
it to the closest RAM block, even if this clock is up to 52 MHz?
I have done it once for slightly slower clocks in Virtex-E and it was
working fine.

Question #2:
There are 2 high speed clocks which we must feed into the design,
2x~156 MHz and one generated internally, 160 MHz.
Each one of these clocks is going to clock a simple one-hot state
machine and a read FIFO port.
Could you give any recommendations on speed grade (and may be
different part) selection, if the approximation of resource usage is
about ~30%, where about ~10% are gonna be clocked with high speed
It's just that I have used before Virtex-E 1000 with 50, 82 and 125
MHz (interface only), as well as XC2V6000-4 and XC2V4000-5 running at
7/19/77 (STS-N), 92 and 125 MHz (GMII). Everything was perfectly
working but i am afraid that due to multiplication of FFs, the
resources usage can start growing and we are not going to be able to
achieve such a frequency.

Sorry for long poem and thank you in advance.


Re: multiple clocking in FPGA
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Can you get rid of all the slow clocks by turning each rising edge
into a clock-enable pulse on a fast clock?

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Re: multiple clocking in FPGA
If you maximum serial clock is 52 MHz, and you have a 160 MHz clock
available, resynchronize the clock and data to the 160 MHz clock, then use
a synchronous edge detect on the resynchronized clock to generate a one
clock wide write enable into your fifo.  Using other than a clock net to
distribute clocks opens you to all sorts of potential timing maladies, not
to mention sensitivity to the place and route solution.

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Re: multiple clocking in FPGA

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There is a maximum skew constraint that can be applied to a clock signal
which makes it possible to use a clock that's not driven by a clock
buffer. Here is an example,

NET "ddr_interface_1_ddr_fifo_1/wr_stb" USELOWSKEWLINES;
NET "ddr_interface_1_ddr_fifo_1/wr_stb" MAXSKEW33%0 ps;

Also 52Mhz is slow enough that you can use both edges of the clock which
would allow you to alternate negative edge stages with positive edge
stages which will allow you to get away with a lot of clock skew.

Generally you want to limit the use of non-clock buffer clocks to things
like the input side of async FIFOs. The FIFOs can be used to transition
between the external clock domains and your master clock domain.

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