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multidimensional arrays in VHDL?

I am trying to covert the following Verilog code to VHDL. I am having issues with converting the arrays to VHDL. Could you please comment on how this should be done module FIFO16x8(DataOut, DataIn, FF, AF, HF, AE, EF, Push, Pop, Dump, Clk); parameter WIDTH = 8; parameter DEPTH = 16; parameter LOG2DEPTH = 4;

input [(WIDTH-1):0] DataIn; output [(WIDTH-1):0] DataOut; output FF, AF, HF, AE, EF; input Push, Pop, Dump, Clk;

wire WE, RE;

reg [(LOG2DEPTH-1):0] Contents, ReadPointer, WritePointer; reg [(WIDTH-1):0] queue[(DEPTH-1):0];

assign FF = (Contents == (DEPTH-1))? 1 : 0; assign AF = (Contents > (DEPTH-3))? 1 : 0; assign HF = (Contents > (DEPTH/2))? 1 : 0; assign AE = (Contents < 3)? 1 : 0; assign EF = (Contents == 0)? 1 : 0;

assign WE = Push && ~FF; assign RE = Pop && ~EF;

assign DataOut = queue[ReadPointer];

always @ (posedge Clk) begin if (Dump == 1) Contents

Reply to
Anuja
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Use,

TYPE queue IS ARRAY(15 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0);

Since your read and write pointers are std_logic_vectors, they cannot be used for indexing into and array. Convert them to integers using the functions in numeric_std package like so

DataOut

Reply to
sudhi

Shouldnt the array be multidimensional? Isnt the array you defined one dimensional?

Reply to
Anuja

I am getting the following error message No feasible entries for subprogram "to_integer".

I HAVE INCLUDED NUMERIC_STD package as follows

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; USE IEEE.numeric_std.ALL;

It also comlained about target of signal assignment is not a signal. So, I defined q_queue of type queue(array) and that was solved.

Reply to
Anuja

Take a look at this for the conversion problem

formatting link

In a fifo you only need a single dimensional array of std_logic_vectors. If the fifo is bit addressable then you could call this declaration a multidimensional array.

-Sudheendra Kadri

Reply to
sudhi

cannot

You do not need "USE IEEE.std_logic_unsigned.ALL;" Instead do a cast t type 'unsigned'...

DataOut

Reply to
RCIngham

In fact, including both is dangerous. Also, std_logic_unisgned is deprecated.

Reply to
comp.arch.fpga

My problem was solved by using the package IEEE.std_logic_unsigned.ALL; and I used the function conv_integer which directly converts the std_logic_vector to integer. In this case i do not have to convert the vector to unsigned.

Thank you all for your help

Anuja

Reply to
Anuja

If you ever go on a VHDL course, I am sure that you will be told that us of the 'std_logic_arith', 'std_logic_signed', 'std_logic_unsigned packages is DEPRECATED, and that you should only use the IEEE Standar

1076.3-1997 'numeric_std' (or 'numeric_bit' if not using 9-level logic package. I strongly advise you to get into this good habit now.
Reply to
RCIngham

Thank you very much for your advise

Reply to
Anuja

I posted code to your message in comp.lang.vhdl. Have a look at it.

Regards, JK

Reply to
JK

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