Hi All,
How to identify the Multi cycle path and the False path in the design. do we need to identify after the Synthesis stage xilinx fpga tool it self will recognize and through as warning or error.
At what stage in the asic flow this multicycle path and False path are identified. How to fix this Multi cycle path and false path in the fpga flow
How it is going to effect the Timing Closure and the Slack of the design.
regards kil
If this is a medium/high budget project I would speak to the Fishtail
If you have to do this manually then start by looking at the most negative slack path and simply plough through the code/schematics to see if that path is false/multicycle or not. It is not going to be easy or quick especially for false path. If you have access to a formal tool or PSL/SVA support for your simulator then you might be able to write a property to check that, for example, and enable pin on the output of a long combinatorial path FF is always stable for more than 1 clockcycle.
Hans.
I think you should have this idea on mind when you make your design. you just use the multi cycle or false path constraint to let this path not so important that the design can avoid the timing violations.
If done manually, it's most likely going to be done incorrectly.
KJ
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.