Hi everyone,
may I ask you a question. I'm trying to find out how to handle multi-cycle paths in VHDL libraries. I'm using Xilinx ISE 9.2i and XST. I have designed a number of modules, all compiled into separate libraries, which I would now like to use in a bigger design. Some of them have multi-cycle paths, so I would like to specify appropriate timing constraints. I know that I can specify from-to (only?) in an .xcf-file, however, that information appears to end up only in the .ngc-netlist, not in the VHDL-library. As opposed to, for example, a maxdelay-constraint, which I can specify as an attribute in the VHDL-source, and which is included in the library and later recognized by P&R. Any help? Thanks a lot, best regards Gunter