Multi-clock / clocking counter

Hello all,

I have a slightly interesting problem here, and I wanted to know if my approach has any hazards which I should be aware of. My design is for a CPLD, if that matters.

I have a binary synchronous counter, I call Master_Counter, that I want to clock at 312.5kHz (1/128th my system clock of 40MHz). I generate my

1/128 Prescale_CLK by picking off the MSB of a 7-bit counter which is clocked at Sys_CLK frequency(40MHz).

In my design, Master_Counter usage is multiplexed -- it will be used to time four separate signals (which are synchronous to the 40MHz Sys_CLK) all 26kHz or below. To be able to select which signal is timed, I route my 4 signals into a 4:1 MUX.

My current approach is to use Prescale_CLK to gate the ENABLE on the counter, with Master_Counter getting clocked from the 40MHz Sys_CLK.

Since I need to time one of the four signals, I am actually ANDing the output of the 4:1 MUX with the Prescale_CLK and that feeds the ENABLE pin on Master_Counter.

From reading the c.a.fpga archives, I *think* this is the correct approach since I've read the CLK input itself should never be gated, only the ENABLE but I would appreciate any commentary.

My other problem is dealing with reset/clear logic which could get complicated, since I need to make sure the counter is reset/ENABLED properly when the MUX is switched (which occurs asynchronous to the four signals). I have seen Mr. Alfke's circuit that allows you to switch asynchronous clocks, I'll look at that again for ideas.

As usual, thanks!

-- Jay.

Reply to
Jay
Loading thread data ...

Thanks for the suggestion!

Best regards.

-- Jay.

Reply to
Jay

I got your email, but I thought I would reply here. CPLD vs. FPGA does not matter as far as I know. If I understand what you are doing, you have a system clock of 40 MHz, but want to use a 312.5 kHz clock to time one of four inputs which switch synchronously with your system clock.

Using the MSB of a prescale counter to use as a 312.5 kHz enable will not work. This pulse will be true for half the period and will enable some 64 system clock pulses each time it is true. You want a pulse that is one clock wide. You can either use a AND function to detect the count of 127 (which may end up being implemented in the carry chain) or use a FF to delay the MSB by one clock and an AND gate and inverter to generate a pulse one clock wide on each rising edge of the MSB. This

312.5 kHz signal can then be AND'd with the output of the MUX to drive your counter enable.
--
Rick "rickman" Collins

rick.collins@XYarius.com
 Click to see the full signature
Reply to
rickman

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.