Hello all,
I have a slightly interesting problem here, and I wanted to know if my approach has any hazards which I should be aware of. My design is for a CPLD, if that matters.
I have a binary synchronous counter, I call Master_Counter, that I want to clock at 312.5kHz (1/128th my system clock of 40MHz). I generate my
1/128 Prescale_CLK by picking off the MSB of a 7-bit counter which is clocked at Sys_CLK frequency(40MHz).In my design, Master_Counter usage is multiplexed -- it will be used to time four separate signals (which are synchronous to the 40MHz Sys_CLK) all 26kHz or below. To be able to select which signal is timed, I route my 4 signals into a 4:1 MUX.
My current approach is to use Prescale_CLK to gate the ENABLE on the counter, with Master_Counter getting clocked from the 40MHz Sys_CLK.
Since I need to time one of the four signals, I am actually ANDing the output of the 4:1 MUX with the Prescale_CLK and that feeds the ENABLE pin on Master_Counter.
From reading the c.a.fpga archives, I *think* this is the correct approach since I've read the CLK input itself should never be gated, only the ENABLE but I would appreciate any commentary.
My other problem is dealing with reset/clear logic which could get complicated, since I need to make sure the counter is reset/ENABLED properly when the MUX is switched (which occurs asynchronous to the four signals). I have seen Mr. Alfke's circuit that allows you to switch asynchronous clocks, I'll look at that again for ideas.
As usual, thanks!
-- Jay.