hi
I think I am close to get it fully working, but some things are still messy
MPMC2 has only verilog but EDK simulation works better in VHDL, so so far all attempts to get the all thing to work on init the onchip memories in simulator still fail
when toplevel is VHDL memory init would work, but mpmc2 verilog doesnt load properly in simulator, or it loads after manual fix, but the it doesnt see the glbl.v :(
when having the toplevel as verilog then the EDK system and MPMC2 and DDR2 simulation models all load properly in simulator, but then I cant init the onchip memories any more.
so what is the proper way to simulate such designs?
Antti