MPMC On EDK

The MPMC DDR-Interface is based on the MIG-Memory Controller. Download at

the "User Guide" (ug086.pdf). See page 331/332: Generic Memory Interface Guidelines.

Daniel

ratemonotonic schrieb:

Hi Daniel ,

Thanks for the links the doc looks good and I am going through it now. Is the MPMC suitable to interface with asynchronous DDR SDRAMS? i.e. the reference board I am using has Micron MT46V16M16FG-75 16Mx16 part which takes min 75mhz clock. the microblaze on the board is running at

50 Mhz, but the board has 75Mhz clock. In the original design an OPB DDR SBRAM controller was used in which there was seperate control for the DDR clock inputs , but MPMC only seems to take the system clock as an input which is my case is 50 Mhz. How do I produce an 75 Mhz DDR clock from MPMC?

Thanks very much , BR Rate

The MPMC can not produce a 75Mhz clock from a 50 Mhz source. But the MPMC supports 1:2 System/PIM clock and memory clock.

See at page 50 of Datasheet MPMC (DS643) near "_Clk".

For example you have a 50Mhz source clock, use clk0 (system clock) and clk2x output of a DCM to produce the 100Mhz memory clock. Do not forget to connect clk0 and clkfb to assure zero phase offset.

Hi Daniel, Thanks a lot ! I sort of see light at the end of the tunnel now with your suggestion! I will let you know when I have tested the setup!

Thanks rate