Hi all,
Up until now, everything I've done has been synced to a single clock running around the FPGA. I now want to add a hardware divider (64 or 32 bit dividend, 32 bit divisor) as a peripheral to the CPU, and it's going to be s...l...o...w - still faster han doing it in s/w of course :-)
A nice way to speed it up then would be to clock the divider circuit at a multiple of the rest of the CPU... Now I've read of things like 'metastability' and advice to 'never use gated clocks' and such, so I was wondering if the following would be safe if the divider clock is running at M times the cpu clock (using a DCM) ?
clock action
0 cpu writes dividend & divisor to divider module input ports +1 cpu sets the 'go' input to divider high and waits for 'rdy'+0.x divider starts (N internal cycles) to perform division
+0.N divider writes result to module output port +0.M divider writes 'rdy' to module output+1 cpu reads result from divider, sets 'go' signal low.
+1.x divider sets 'rdy' low since 'go' has gone lowThe syntax for the clock here is that numbers before the '.' represent CPU clocks, numbers after represent divider clocks. The 'x' in stages 3 and 7 just represents the fact that the divider clock may be a few periods ahead (in internal cycles) of the cpu clock - not really important, also the syntax '+0.N' really means +(N/M).(N%M) since N/M is highly likely to be >1...
Since the divider waits for M internal clocks (1 whole cpu clock) after writing the result and before writing 'rdy', doesn't that mean the result will be stable before the cpu reads it ? Is M clocks delay sufficient ? Would less do ?
Or is the whole idea a complete idiocy and should I scuttle back to completely synchronous designs [grin] ?
Thanks in advance for any help :-)
Simon.