State machines and synchronization.
The background is that I'm working on this PWM unit that uses a serial shift register to hold the pulse "width" data. The original code goes something like:
-- process to manage clocking in the data sr: process (sdata_in, sclock, reset) is begin if (reset = '1') then serial_data
OK. We are receiving and shifting in the pwm bitstream into parallel bytes.
Take sdata_in out of the sensitivity list and you have a synchronous process that will sim and synth the same way.
Hmmm. Why are we making bytes in the first place?
-_______--______----____-------_
Don't we just want to preset a counter while the data is high and count down while it is low?
-- Mike Treseler
I see that you are using a < comparator to generate pwm. Although this works OK it takes quite a lot of logic to implement ( see the RTL schematics and it will all become clear to you ). Some time ago i needed a six chanel 8 bit pwm generator. I used the 95108, and with < comparators it wouldn't fit. So I used annother method - compare match. The basic idea is that you don't need to know if the pwm data is less that set data, just if they are equal ( == comparator ), which takes a lot less logic. I created a counter entitiy with clk input and
8 bit counter output. This counter is common to all six pwm generators. Although you need a serial load generator, I am stil including my code for a parallel load. But is should be easy for you to modify it into a serial.str is strobe signal for the latch Din is 8 bit parallel data input duty_cycle is the latched input data Cin is the 8 bit counter input 8 Clk is the main clock, also used by the counter pwm is the PWM output
-- data latch p00: process(rst,str) begin if rst = '1' then duty_cycle
It looks like that would cause a discontinuity from 254/256 duty to
256/256. I guess that would bother me more that not getting to 100% on.Since you probably have a high speed clock for the PWM, I would probably just use that for everything, as long as your serial clock was enough lower, then you would have a fully synchonous system which would avoid a number or problems.
As others have pointed out there are some simpler ways to generate PWM:
one is the = comparator and SR flipflop
There is also a way for N bit PWM that uses a N+1 bit accumulator where the N+1 bit is used as the PWM output.
This design has the advantage that it does not require a reference counter and that the input can be changed asyncronously relative to the PWM period and the output will be correct (its kind of an intergrating PWM source)
The comparator method has the advantage that if you want to filter the PWM (say to generate a audio signal) you can easily generate interleaved PWM by bit reversing any desired number of reference count MSBs
Peter Wallace
Wow! The light bulb goes on! That's a great idea, a simple set of XOR gates feeding an AND gate make for a match compare. I'll no doubt run into a bit of trouble later when I'm trying to run the sequences "out" of phase, but I can do that brute force with a simple adder. Thanks George!
--Chuck
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