After I found out that I couldn't syntesize a lot of the verilog code (
module counter32(in,reset,out); input [0:0] in; input reset; output [4:0] out;
always @(posedge in) begin /* i've seen sample code include reset here, dont know why though */ if (!reset) out = out + 1; end
always @(posedge reset) out = 5'b00000;
endmodule
module latch32(in,out,enable,signal); input [5:0] in; output [31:0] out; input enable; input signal; integer N;
always @(posedge enable) out[in] = signal;
endmodule
module counterLatch32(in,reset,enable,signal,out); input [0:0] in; input [0:0] reset; input [0:0] enable; input [0:0] signal; output [31:0] out;
wire [4:0] select; reg [31:0] out;
module counter32(in, reset, select); module latch32(select, out, enable, signal);
endmodule