Metastability occurs when we don't respect setup and/or hold times. But what does happen when the input for the flip-flop is a DC signal between Vil and Vih? (Or it changes so slowly that looks like a constant.)
My guess is there is a voltage, let's say Vth, that: If Vin < Vth => DOUT = 0 after a delay If Vin > Vth => DOUT = 1 after a delay The delay grows as Vin approximates to Vth.
Am I right?
Luiz Carlos