I am designing a state machine that will be fit into a CPLD (Xilinx XC95xx). The state machine needs to wait certain number of clockes here and there ( for example, 80 clockes here, and 160 clockes there ). If I design everthing with hand, I whould choose structured state machine; that is, a state machine plus a counter. But since I am using VHDL, and the compiler would take care of everything, I think I might be able to make a monolithic state machine with the counter built in ( that is, to add 80 states here, and 160 states there ). Excluding the counter, the state machine has about
100 states.My question is, which approach is better, for a CPLD? The monolithic design will require less FF's, maybe. Have you guys met this question in your projects?