Module integration, odd state machine behaviour (verilog), etc!

Hiya...

I'm using Altera Quartus II, Pluto II (see fpga4fun.com, its one of their boards - GREAT site! - it's an Altera Cyclone), Verilog, you know the deal ;)

I'm trying to integrate all my modules (for the purposes of this I have a compass module, which reads a direction over I2C, and a motor controller - PWM, reversible).

These are held within a module called 'scanner'.

Snippet'ed code in question:

-----------------start of code--------------

input clk; input clk100khz; output hwSonarTrigger; input hwFrontEcho; input hwRearEcho; inout hwCompassSCL; inout hwCompassSDA; output hwSpinA; output hwSpinB; output [1:0] state; // for debugging purposes

// ...snip...

wire [7:0] compassDirection; wire compassDirectionUpdated;

reg [7:0] spinSpeed; reg spinDirection; reg spinEnabled;

// ...snip...

reg [7:0] baseCompassDirection;

wire [7:0] clockwiseDistance = baseCompassDirection - compassDirection; wire [1:0] antiClockwiseDistance = compassDirection - baseCompassDirection;

reg [1:0] state = 0;

// basic operation: // state 0 initialises, resets, forwards to state 1 // state 1 waits until a compass direction has been obtained, records the direction in baseCompassDirection, and moves into state 2 // state 2 compares the stored compass direction against the measured, and sets the motor controller to correct for movement

always @(posedge clk) begin if ( state == 0 ) begin spinEnabled

Reply to
kierenj
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Hmm, you left out the module declaration -- at least I hope you have one!

And then what? You never transistion out of state 2, is that intentional? Shouldn't you at least go back to state 1 every once in a while?

Suggestions:

- Show us *all* the code as often the bugs are not in what's posted

- Use parameter INIT = 0; etc and give the states symbolic names

- Use a case statement instead case state INIT: begin ... endcase

- Keep the names the same inside and outside the module. That lessens confusion and the change of mispelling (which btw is silently assumed to be an implicitly declared net).

Cheers, Tommy

Reply to
Tommy Thorn

Hi there,

Originally I didnt include all the code since there are several modules, and lots of lines in them. I've changed the state machine to use a case statement and symbolic names. (Yes, it is intentional, after the initial power-up reading I'd like it to go through the states 0, 1, and stay at 2). The full source is attached below.

////////////////////////////////////////////////

module scanner(clk, clk100khz, hwCompassSCL, hwCompassSDA, hwSpinA, hwSpinB, state);

//////////////////////////////////////////////// // SECTION: Inputs / Outputs //////////////////////////////////////////////// input clk; input clk100khz; inout hwCompassSCL; inout hwCompassSDA; output hwSpinA; output hwSpinB; output [1:0] state;

////////////////////////////////////////////////

wire [7:0] compassDirection; wire compassDirectionUpdated;

reg [7:0] spinSpeed; reg spinDirection; reg spinEnabled;

////////////////////////////////////////////////

reg [7:0] baseCompassDirection;

wire [7:0] clockwiseDistance = baseCompassDirection - compassDirection; wire [1:0] antiClockwiseDistance = compassDirection - baseCompassDirection;

reg [1:0] state = 0;

////////////////////////////////////////////////

parameter INIT = 0; parameter ACQUIRE = 1; parameter MONITOR = 2;

////////////////////////////////////////////////

always @(posedge clk) begin case ( state ) INIT: begin spinEnabled

Reply to
kierenj

I suggest you code your FSM with an asynchronous reset pointing to INIT. Otherwise, there is no state leading to Init, and the extremely clever sythesizer in Quartus II might have noticed...

- Never an FSM without a reset.

- Do NOT initialize variables at declaration ! /most/ synthesis tools will simply ignore this.

and make sure you don't mix up signals from different clock domains without proper resync.

Hope this helps,

Bert Cuzeau

Reply to
info_

Aah brilliant, nowhere near the amount of warnings/errors - I'll download it into my board and see what happens!

I had been advised that async resets were bad, and that you can assume that registers will ALWAYS power-up with 0. When Quartus complained that it was making registers high because I hadn't specified a power-up value, I thought I'd try initialisers...

Thanks.. I'll let you know how it goes! Cheers!

Reply to
kierenj

And that is true and I disagree with the reset advise. It usually a waste of resources if you don't need it. I in particular *never* use asynchronous reset, thought I can see the use in ASICs.

Initializers are ignored for synthesis -- You used non-zero initializers? I usually add zero initializers to make simulation match what you get in the FPGA.

Tommy

Reply to
Tommy Thorn

Enable FF on a three state bus might need one. Or a control line that needs to be set to a level when the clock isn't running.

-- Phil Hays Phil-hays at posting domain (- .net + .com) should work for email

Reply to
Phil Hays

All went well... did the job marvellously. I can use this knowledge to take over the world... much appreciated. Ta

Reply to
kierenj

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