Modifying opb_bram under EDK

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
I'm trying to create a customized BRAM module (memory redundancy,
checkbits) However, the BRAM included in the EDK cannot be simply
modified (no hdl in the ip core directory). Does anyone know of anyways
to modify it?

Re: Modifying opb_bram under EDK
Quoted text here. Click to load it

The opb_bram is for use with the block ram inside the FPGA. Are you
really planning to add redundancy and checkbits to that? If so, I would
wonder why. If the BRAM can be corrupted, then so can the rest of the
FPGA, so are you also adding error detection and correction to the rest
of the FPGA?

My EDK does come with source for the opb_bram, assuming you are
referring to
EDK6.3/hw/XilinxProcessorIPLib/pcores/opb_bram_if_cntlr_v1_00_a/hdl/vhdl
So I cannot imagine why you wouldn't have it.

Re: Modifying opb_bram under EDK
I'm talking about the actual bram, ot the controller.

Quoted text here. Click to load it

Re: Modifying opb_bram under EDK
Quoted text here. Click to load it

The code for this is generated on the fly in an EDK project. It should
end up being located in project_dir/hdl/elaborate/...

So I guess in your case, create a simple project with the desired block
ram, then copy and modify the generated file.


Site Timeline