Hi,
I'm working on a small research project, for which I'd really like to be able to modify a post-PAR Xilinx design. Specifically, I'd like to remove routing information for a single net, add have it rerouted with new timing constraints.
So far I have come accross two possible ways of realistically doing this, but they both have problems.
- Use JBits
The problem with using JBits is that it doesn't look like it has a router advanced enough to (among other things) take into account timing constraints. Also the bitfile format loses all symbolic naming information, which is something it would be very helpful to use to guide this process.
- Modify the PAR'ed NCD directly a'la FPGA Editor but automated
I came accross XDL which looked like it might do the trick. So I tried a simple experiment:
- PAR a simple design to NCD format
- convert the NCD to XDL
- remove the PIP information for a single net in the XDL file
- convert the XDL back to NCD (including compensating for the lost ISET information as in Xilinx Answer record #17204)
- re-run PAR on the original (unplaced) NCD using the modified ncd->xdl->ncd file as a guide in 'exact' guide mode.
This sort of works, but the guide report suggests that there isn't a
100% match between the guide file and the original NCD (see below), and seems to think that 129 signals rather than 1 need re-routing. This really isn't ideal for me, as I'd like to leave as much of the initially PAR'ed design intact as possible.It'd be really good if I could get this technique to work, but I can't understand why there are mismatches between the two NCD files and more than one net that needs re-routing. I also found that even if I omitted stages 2-4 from my expt. above and just used the fully PARed NCD as a guide, there are still mis-matches between this and the unPARed NCD.
Does anyone have any comments or suggestions on how I could refine this process, or an alternate method I could use?
Thanks,
- Jake
Snippet of output from the guided PAR:
Xilinx Place and Route Guide Results File =========================================
Guide Summary Report:
Design Totals: Components: Name matched: 1873 out of 1873 100%
Total guided: 1873 out of 1873 100%
Signals: Rejected Implicit/Internal: 3046 out of 7238 Name matched: 4192 out of 4192 100% Total guided: 4191 out of 4192 99% Total connections guided: 8582
Guide file: "modified_xdl.ncd" Guide mode: "exact"
Components: Name matched: 1873 out of 1873 100% Total guided: 1873 out of 1873 100%
Signals: Name matched: 4192 out of 7238 57% Total guided: 4191 out of 4192 99% Total connections guided: 8582
... Phase 1: 129 unrouted; REAL time: 8 secs
Phase 2: 0 unrouted; REAL time: 31 secs ...