Modify POF with new ESB (ROM) content?

I can build my project and after that quickly build the hex/mif and merge it into the sof. Why do you think this is so bad?

Petter

quit simple

if you want to deliver a BITFILE only and allow the client to change the software but not the FPGA bit file itself.

this is VERY simple with Xilinx tools and IMPOSSIBLE with Altera tools

How many times that needs to be explained?

there is not even need to have all tools installed for bitstream update only the C compiler and merge tool

Antti

The client will still need the SDK and FPGA tools from the vendor.

Or do you look at the bit-file as a method of protecting your HDL code from your customer?

Petter

good god... how can it be that you dont understand...

the ELF to BIT merge is much simpler than the cdb_mif update

this is the reason why XILINX is doing it that way. this is how ALL FPGA vendors should do it, at least all FPGA VENDORS that offer soft-core solutions.

sure its my opinion, but I am sure i am not the only one, who would like to see

DATA2BIT tools (aka elf to programming file merge) for other FPGAs too, not only for Xilinx.

Antti

Sounds like simple common sense - what is it that prevents Altera from offering this ? - and why did they miss this obvious flow ?

-jg

I do understand the difference between the two. I've used both tools.

I know that it's simpler. But when you have the RTL source there is no practical difference. At least it's not for me. It only takes a couple seconds to run the merge in each case.

But if you have lost the source (like the OP) or will not give some

Petter

I've tried to explain this to Altera reps several times, and they just don't get it that their tool is much less capable than Xilinx's in this area. It's effectively like saying that you have to have design documents for your entire PC on hand if you want to install an updated BIOS...

There are some hints out there that it may not be too hard to reverse engineer

B.t.w two questions:

- can anybody give an example commandline for a real world DATA2MEM example?

- can any FPGA family BRAM be written by JTAG directly without upsetting the rest of the FPGA configuration?

It's been a while (don't have access to ISE at the moment), but I've usually done this through bitinit, something like:

bitinit system.mhs -bm system.bmm -pe ppc405_0 executable.elf -bt old.bit -o new.bit

Somebody else probably have a similar data2mem command laying around somewhere.

That's what I normally do with the NIOS software. It depends on how your application will handle that your software is replaced with a new version on-the-fly.

Petter