1. Home
  2. Field-Programmable Gate Arrays
  3. ModelSim XE problems with a VHDL coregen in a Virtex 5

ModelSim XE problems with a VHDL coregen in a Virtex 5

I'm getting a fatal error when I try and simulate a Virtex 5 VHDL project with a block memory core built with coregen. The Virtex 5 Coregen is only allowing Block Memory Generator V2.6 to be used. I see these files in the $XILINX\vhdl\src\XilinxCoreLib directory, but they do not show up in the ModelSim workspace under xilinxcorelib which only goes up to blk_mem_gen_v2_4. Does anyone know what I need to do to get ModelSim to start using these (newer) block mem gen files?

Thanks

Dan

Reply to
Dan K
Loading thread data ...

Have you recompiled the libraries after the last IP update and/or SP installation? Maybe the Block Memory Generator V2.6 was added in the latest IP update and it will not show up in ModelSim unless you recompile the files in $XILINX\vhdl\src\XilinxCoreLib.

You can do that with "compxlib" on a command line, but I think there's a wizard for this in the ISE-GUI somewhere now.

HTH, Sean

--
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...
Reply to
Sean Durkin

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.