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ModelSim Waveform naming question

I am using ModelSim SE and was wondering if there is a way to make a waveform display mnemonics. I am simulating a state machine and it would be convenient to have the waveform display the state name instead of the binary/hex of the state. I looked all over the documentation and didn't find anything.

The module is written in verilog and the states are parameterized. NC- Sim had an easy way to map numerical values to text. You create the mapping and then can apply it to any waveform. I just haven't found an easy way to do this in ModelSim. It is probably staring me in the face!

Reply to
motty
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motty schrieb:

Hi motty do you have enumerated types in verilog? e.g. type fsm_state_type is (start, action1, action2,...,end);

If so, you could use (or assign ) these to a signal that corresponds to the state of your FSM. This signal can be displayed in the modelsim wave window as readable text.

have a nice simulation Eilert

Reply to
backhus

Another possibility that I've seen in some situations is to set a signal to a certain string in the state machine as in:

always @(posedge clk) if(rst) begin state_r

Reply to
Andreas Ehliar

It's not staring you in the face at all - it's a little tricky to find - but check out the online help for the "virtual type" and "virtual function" commands, and you'll get what you need.

To answer backhus: no, you don't have enumerations in Verilog (although they do exist in SystemVerilog).

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Reply to
Jonathan Bromley

Thanks for the replies. Jonathan, that did the trick. Hmmm, seems a bit more involved than with NC-Sim. But ModelSim seems to be the better simulator for us...at least with respects the FPGA/Xilinx simulation.

Reply to
motty

And somewhat cumbersome to use as well, I don't know why they haven't included anything more automatic.

Anyway, this thread got me thinking that it shouldn't be that hard to write a TCL script that will automatically add a virtual function and type for you if you just select the state parameters and the state variables. I don't know why I haven't thought about doing it earlier...

Anyway, I've just spent the evening writing such a script and it seems to be working quite ok. If anyone is interested they can find it at

formatting link
(look for stateenumerate.tcl).

/Andreas

Reply to
Andreas Ehliar

Reply to
Andreas Ehliar

I've started using the SystemVerilog enumerated types; these are also accepted by Synplify. Synplify will also display the state names in its state machine diagrams.

For Verilog 2001, I set up a separate string as described in another post but I put it in its own combinational process and then display it as a string in Modelsim. E.g.,

reg [32*8-1:0] StateStr; parameter IDLE=1,START=2; always@(State) case(State) IDLE: StateStr="IDLE"; START: StateStr="START"; endcase

-Kevin

Reply to
Kevin Neilson

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