modelsim Warning "VIOLATION ON D WITH RESPECT TO CLK"

Simulators do have bugs, but in general you should trust the simulator more than your own newly developed code.

Pretty clear description, you're violating the setup time of the flip flop. In post-route simulation this is frequently caused by having a design input signal transition at the wrong time relative to the clock or if you are trying to run the design at a clock speed faster than the design can handle (i.e. timing analysis indicates a max frequency of 95 MHz and post route-sim is running the clock at 100 MHz. In any case, it is pointless to try to run a post-route sim before you have completed static timing analysis of your design. Also make sure that your testbench code is transitioning the design inputs at a time relative to the clock that meets the setup and hold time requirements as computed by static timing analysis and not just at 'the rising edge of the clock'.

KJ

Hi,

I think in this case you haven't started the simulation with the delay file. When doing post layout simulation, the netlist will have checks for hold and setup timings and without any net delays, you will most likely get this kind of errors.

If you just do "vsim" then you will not get any delay file into which could explain your warning messages. You have to add "-sdfmax " if you want to run with max delays which is the normal case.

You can find more on how to do VITAL/verilog timing simulations in the modelsim manual.

Hope this helps Göran

I have other warning in the .log but i don't see that in the simulation. ¿can i trust in this simulation?

Warning: */DFF SETUP High VIOLATION ON D WITH RESPECT TO CLK; # Expected := 0.8 ns; Observed := 0 ns; At : 179.2 ns

thanks.